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[/] [sdram_controller/] [trunk/] [sdram_reader.vhd] - Diff between revs 6 and 7

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---- Uncomment the following library declaration if instantiating
 
---- Uncomment the following library declaration if instantiating
 
---- any Xilinx primitives in this code.
 
---- any Xilinx primitives in this code.
 
--library UNISIM;
 
--library UNISIM;
 
--use UNISIM.VComponents.all;
 
--use UNISIM.VComponents.all;
 
 
 
 
 
-- I strongly suggest you run this in the post-PAR simulator first and then start making changes to it
 
-- I strongly suggest you run this in the post-PAR simulator first and then start
 
--  after looking at what goes on at the post-PAR level. Don't say I didn't warn you. 
--  making changes to it after looking at what goes on at the post-PAR level. Don't
 
-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it won't fit into the IOBs
 
--  say I didn't warn you. 
--  with the ODDR2 primitives. I decided the ODDR2s were more important to keep.
 
-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it
 
-- I'm just capturing the front side of the burst, and letting the back side of the burst fall on the
 
--  won't fit into the IOBs with the ODDR2 primitives. I decided the ODDR2s were
 
--  floor. If you want to support both sides of the 2 burst or bigger bursts, you'll need to rework this.
 
--  more important to keep.
 
 
 
-- I'm just capturing the front side of the burst, and letting the back side of
 
 
 
--  the burst fall on the floor. If you want to support both sides of the 2 burst
 
 
 
--  or bigger bursts, you'll need to rework this.
 
entity sdram_reader is
 
entity sdram_reader is
 
        port(
 
        port(
 
                clk270 : in std_logic;
 
                clk270 : in std_logic;
 
                rst    : in std_logic;
 
                rst    : in std_logic;
 
                dq     : in std_logic_vector(15 downto 0);
 
                dq     : in std_logic_vector(15 downto 0);

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