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[/] [sdram_controller/] [trunk/] [sdram_writer.vhd] - Diff between revs 6 and 7

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---- Uncomment the following library declaration if instantiating
 
---- Uncomment the following library declaration if instantiating
 
---- any Xilinx primitives in this code.
 
---- any Xilinx primitives in this code.
 
--library UNISIM;
 
--library UNISIM;
 
--use UNISIM.VComponents.all;
 
--use UNISIM.VComponents.all;
 
 
 
 
 
-- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as careful with the
 
-- Uses ODDR2 registers to generate the required DDR signals. Don't have to be as
 
--  timings as with sdram_reader, but you need to be able to feed the ODDR2's within their setup
 
--  careful with the timings as with sdram_reader, but you need to be able to feed
 
--  and hold windows. Or very very hilarious things will occur. Post-PAR simulation is good for
 
--  the ODDR2's within their setup and hold windows. Or very very hilarious things
 
--  getting a feel for the (mis)timings.
 
--  will occur. Post-PAR simulation is good for getting a feel for the
 
 
 
--  (mis)timings.
 
entity sdram_writer is
 
entity sdram_writer is
 
        port(
 
        port(
 
                clk    : in std_logic;
 
                clk    : in std_logic;
 
                clk090 : in std_logic;
 
                clk090 : in std_logic;
 
                clk180 : in std_logic;
 
                clk180 : in std_logic;

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