| Line 43... |
Line 43... |
rst : in std_logic;
|
rst : in std_logic;
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addr : in std_logic;
|
addr : in std_logic;
|
data_o : in std_logic_vector(7 downto 0);
|
data_o : in std_logic_vector(7 downto 0);
|
dqs : out std_logic_vector(1 downto 0);
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dqs : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dm : out std_logic_vector(1 downto 0);
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dq : out std_logic_vector(15 downto 0);
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dq : out std_logic_vector(15 downto 0)
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done : out std_logic
|
|
);
|
);
|
end sdram_writer;
|
end sdram_writer;
|
|
|
architecture impl of sdram_writer is
|
architecture impl of sdram_writer is
|
|
|
| Line 94... |
Line 93... |
signal dq_falling : std_logic_vector(15 downto 0) := x"0000";
|
signal dq_falling : std_logic_vector(15 downto 0) := x"0000";
|
|
|
signal data_out : std_logic_vector(15 downto 0);
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signal data_out : std_logic_vector(15 downto 0);
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signal mask_out : std_logic_vector(1 downto 0);
|
signal mask_out : std_logic_vector(1 downto 0);
|
|
|
signal writer_dqs_done : std_logic := '0';
|
|
signal writer_dm_done : std_logic := '0';
|
|
|
|
begin
|
begin
|
|
|
ODDR2_dqs: oddr2_2
|
ODDR2_dqs: oddr2_2
|
port map(
|
port map(
|
Q => dqs,
|
Q => dqs,
|
| Line 146... |
Line 142... |
process (clk180,rst)
|
process (clk180,rst)
|
begin
|
begin
|
if (rst = '1') then
|
if (rst = '1') then
|
dqs_fsm_r <= '0';
|
dqs_fsm_r <= '0';
|
dqs_fsm_f <= '0';
|
dqs_fsm_f <= '0';
|
writer_dqs_done <= '0';
|
|
writer_dqs_state <= STATE_WRITER_DQS_0;
|
writer_dqs_state <= STATE_WRITER_DQS_0;
|
elsif (rising_edge(clk180)) then
|
elsif (rising_edge(clk180)) then
|
case writer_dqs_state is
|
case writer_dqs_state is
|
when STATE_WRITER_DQS_0 =>
|
when STATE_WRITER_DQS_0 =>
|
dqs_fsm_r <= '0';
|
dqs_fsm_r <= '0';
|
| Line 161... |
Line 156... |
dqs_fsm_f <= '0';
|
dqs_fsm_f <= '0';
|
writer_dqs_state <= STATE_WRITER_DQS_DONE;
|
writer_dqs_state <= STATE_WRITER_DQS_DONE;
|
when STATE_WRITER_DQS_DONE =>
|
when STATE_WRITER_DQS_DONE =>
|
dqs_fsm_r <= '0';
|
dqs_fsm_r <= '0';
|
dqs_fsm_f <= '0';
|
dqs_fsm_f <= '0';
|
writer_dqs_done <= '1';
|
|
writer_dqs_state <= STATE_WRITER_DQS_DONE;
|
writer_dqs_state <= STATE_WRITER_DQS_DONE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
| Line 179... |
Line 173... |
if (rst = '1') then
|
if (rst = '1') then
|
dm_rising <= "11";
|
dm_rising <= "11";
|
dq_rising <= x"0000";
|
dq_rising <= x"0000";
|
dm_falling <= "11";
|
dm_falling <= "11";
|
dq_falling <= x"0000";
|
dq_falling <= x"0000";
|
writer_dm_done <= '0';
|
|
writer_dm_state <= STATE_WRITER_DM_0;
|
writer_dm_state <= STATE_WRITER_DM_0;
|
elsif (rising_edge(clk)) then
|
elsif (rising_edge(clk)) then
|
case writer_dm_state is
|
case writer_dm_state is
|
when STATE_WRITER_DM_0 =>
|
when STATE_WRITER_DM_0 =>
|
dm_rising <= "11";
|
dm_rising <= "11";
|
| Line 200... |
Line 193... |
writer_dm_state <= STATE_WRITER_DM_DONE;
|
writer_dm_state <= STATE_WRITER_DM_DONE;
|
|
|
when STATE_WRITER_DM_DONE =>
|
when STATE_WRITER_DM_DONE =>
|
dm_rising <= "00";
|
dm_rising <= "00";
|
dm_falling <= "00";
|
dm_falling <= "00";
|
writer_dm_done <= '1';
|
|
writer_dm_state <= STATE_WRITER_DM_DONE;
|
writer_dm_state <= STATE_WRITER_DM_DONE;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
done <= writer_dqs_done and writer_dm_done;
|
|
|
|
end impl;
|
end impl;
|
|
|
No newline at end of file
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No newline at end of file
|
