URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [BFMs/] [SGMII_altera/] [testbench/] [model/] [timing_adapter_32.v] - Diff between revs 9 and 20

Rev 9	Rev 20
Line 5...	Line 5...
`//`	`//`
`// $RCSfile: timing_adapter_32.v,v $`	`// $RCSfile: timing_adapter_32.v,v $`
`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/timing_adapter_32.v,v $`	`// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/testbench/models/verilog/ethernet_model/gen/timing_adapter_32.v,v $`
`//`	`//`
`// $Revision: #1 $`	`// $Revision: #1 $`
`// $Date: 2011/11/10 $`	`// $Date: 2012/06/21 $`
`// Check in by : $Author: max $`	`// Check in by : $Author: swbranch $`
`// Author : SKNg/TTChong`	`// Author : SKNg/TTChong`
`//`	`//`
`// Project : Triple Speed Ethernet - 10/100/1000 MAC`	`// Project : Triple Speed Ethernet - 10/100/1000 MAC`
`//`	`//`
`// Description : (Simulation only)`	`// Description : (Simulation only)`