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module mAltA5GXlvds (
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module mAltA5GXlvds (
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input i_SerRx,
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input i_SerRx,
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output o_SerTx,
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output o_SerTx,
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input i_RefClk125M,
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input i_RefClk125M,
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output o_CoreClk,
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output o_RxClk,
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output o_TxClk,
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input i_GxBPwrDwn,
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input i_GxBPwrDwn,
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input i_XcverDigitalRst,
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input i_XcverDigitalRst,
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output o_PllLocked,
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output o_PllLocked,
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output o_SignalDetect,
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output o_SignalDetect,
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.i_ForceDisparity (i_TxForceNegDisp),
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.i_ForceDisparity (i_TxForceNegDisp),
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.i_Disparity (~i_TxForceNegDisp), //1 is positive, 0 is negative
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.i_Disparity (~i_TxForceNegDisp), //1 is positive, 0 is negative
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.o10_Dout (w10_txdata), //abcdeifghj
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.o10_Dout (w10_txdata), //abcdeifghj
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.o_Rd (o_RunningDisparity),
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.o_Rd (o_RunningDisparity),
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.o_KErr (),
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.o_KErr (),
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.i_Clk (w_RxClk),
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.i_Clk (w_TxClk),
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.i_ARst_L (~i_XcverDigitalRst));
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.i_ARst_L (~i_XcverDigitalRst));
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mDec8b10bMem u8b10bDec(
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mDec8b10bMem u8b10bDec(
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.o8_Dout (o8_RxCodeGroup), //HGFEDCBA
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.o8_Dout (o8_RxCodeGroup), //HGFEDCBA
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.o_Kout (o_RxCodeCtrl),
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.o_Kout (o_RxCodeCtrl),
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.tx_inclock (w_TxSerClk),
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.tx_inclock (w_TxSerClk),
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.tx_enable (w_TxEnClk),
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.tx_enable (w_TxEnClk),
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.tx_out (o_SerTx));
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.tx_out (o_SerTx));
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mAltLvdsPll uAltTxPll(
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mAltLvdsPll uAltTxPll(
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.refclk (w_RxClk), // refclk.clk
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.refclk (i_RefClk125M), // refclk.clk
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.rst (w_PorRst), // reset.reset
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.rst (w_PorRst), // reset.reset
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.outclk_0 (w_TxSerClk), // outclk0.clk
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.outclk_0 (w_TxSerClk), // outclk0.clk
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.outclk_1 (w_TxEnClk), // outclk1.clk
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.outclk_1 (w_TxEnClk), // outclk1.clk
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.outclk_2 (w_TxClk), // outclk2.clk
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.outclk_2 (w_TxClk), // outclk2.clk
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.locked (w_TxLocked) // locked.export
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.locked (w_TxLocked) // locked.export
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);
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);
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reg [9:0] r10_txdata0;
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always@(posedge w_TxClk)
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always@(posedge w_TxClk)
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r10_txdata <= w10_txdata;
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r10_txdata <= w10_txdata;
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assign o_CoreClk = w_RxClk;
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assign o_RxClk = w_RxClk;
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assign o_TxClk = w_TxClk;
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reg [7:0] r8_PorTmr;
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reg [7:0] r8_PorTmr;
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assign w_PorRst = ~(&r8_PorTmr);
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assign w_PorRst = ~(&r8_PorTmr);
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always@(posedge i_RefClk125M)
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always@(posedge i_RefClk125M)
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begin
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begin
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