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[/] [sgmii/] [trunk/] [src/] [mAltGX/] [mAltArriaVlvdsRx.v] - Diff between revs 15 and 16

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Rev 15 Rev 16
Line 12... Line 12... 
//                      altera_mf
 
//                      altera_mf
 
// ============================================================
 
// ============================================================
 
// ************************************************************
 
// ************************************************************
 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
//
 
//
 
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
 
// 12.0 Build 263 08/02/2012 SP 2.dp9 SJ Full Version
 
// ************************************************************
 
// ************************************************************
 
 
 
 
 
 
 
 
 
//Copyright (C) 1991-2012 Altera Corporation
 
//Copyright (C) 1991-2012 Altera Corporation
 
//Your use of Altera Corporation's design tools, logic functions 
//Your use of Altera Corporation's design tools, logic functions
Line 35... Line 35... 
 
 
 
 
// synopsys translate_off
 
// synopsys translate_off
 
`timescale 1 ps / 1 ps
 
`timescale 1 ps / 1 ps
 
// synopsys translate_on
 
// synopsys translate_on
 
module mAltArriaVlvdsRx (
 
module mAltArriaVlvdsRx (
 
        pll_areset,
 
        rx_cda_reset,
 
        rx_channel_data_align,
 
        rx_channel_data_align,
 
        rx_in,
 
        rx_in,
 
        rx_inclock,
 
        rx_inclock,
 
 
 
        rx_reset,
 
        rx_divfwdclk,
 
        rx_divfwdclk,
 
        rx_locked,
 
        rx_locked,
 
        rx_out,
 
        rx_out,
 
        rx_outclock);
 
        rx_outclock);
 
 
 
 
 
        input     pll_areset;
 
        input   [0:0]  rx_cda_reset;
 
        input   [0:0]  rx_channel_data_align;
 
        input   [0:0]  rx_channel_data_align;
 
        input   [0:0]  rx_in;
 
        input   [0:0]  rx_in;
 
        input     rx_inclock;
 
        input     rx_inclock;
 
 
 
        input   [0:0]  rx_reset;
 
        output  [0:0]  rx_divfwdclk;
 
        output  [0:0]  rx_divfwdclk;
 
        output    rx_locked;
 
        output    rx_locked;
 
        output  [9:0]  rx_out;
 
        output  [9:0]  rx_out;
 
        output    rx_outclock;
 
        output    rx_outclock;
 
 
 
 
Line 65... Line 67... 
        wire  rx_outclock = sub_wire3;
 
        wire  rx_outclock = sub_wire3;
 
 
 
 
 
        altlvds_rx      ALTLVDS_RX_component (
 
        altlvds_rx      ALTLVDS_RX_component (
 
                                .rx_in (rx_in),
 
                                .rx_in (rx_in),
 
                                .rx_inclock (rx_inclock),
 
                                .rx_inclock (rx_inclock),
 
                                .pll_areset (pll_areset),
 
                                .rx_reset (rx_reset),
 
 
 
                                .rx_cda_reset (rx_cda_reset),
 
                                .rx_channel_data_align (rx_channel_data_align),
 
                                .rx_channel_data_align (rx_channel_data_align),
 
                                .rx_divfwdclk (sub_wire0),
 
                                .rx_divfwdclk (sub_wire0),
 
                                .rx_locked (sub_wire1),
 
                                .rx_locked (sub_wire1),
 
                                .rx_out (sub_wire2),
 
                                .rx_out (sub_wire2),
 
                                .rx_outclock (sub_wire3),
 
                                .rx_outclock (sub_wire3),
 
                                .dpa_pll_cal_busy (),
 
                                .dpa_pll_cal_busy (),
 
                                .dpa_pll_recal (1'b0),
 
                                .dpa_pll_recal (1'b0),
 
 
 
                                .pll_areset (1'b0),
 
                                .pll_phasecounterselect (),
 
                                .pll_phasecounterselect (),
 
                                .pll_phasedone (1'b1),
 
                                .pll_phasedone (1'b1),
 
                                .pll_phasestep (),
 
                                .pll_phasestep (),
 
                                .pll_phaseupdown (),
 
                                .pll_phaseupdown (),
 
                                .pll_scanclk (),
 
                                .pll_scanclk (),
 
                                .rx_cda_max (),
 
                                .rx_cda_max (),
 
                                .rx_cda_reset (1'b0),
 
 
 
                                .rx_coreclk (1'b1),
 
                                .rx_coreclk (1'b1),
 
                                .rx_data_align (1'b0),
 
                                .rx_data_align (1'b0),
 
                                .rx_data_align_reset (1'b0),
 
                                .rx_data_align_reset (1'b0),
 
                                .rx_data_reset (1'b0),
 
                                .rx_data_reset (1'b0),
 
                                .rx_deskew (1'b0),
 
                                .rx_deskew (1'b0),
Line 95... Line 98... 
                                .rx_dpll_reset (1'b0),
 
                                .rx_dpll_reset (1'b0),
 
                                .rx_enable (1'b1),
 
                                .rx_enable (1'b1),
 
                                .rx_fifo_reset (1'b0),
 
                                .rx_fifo_reset (1'b0),
 
                                .rx_pll_enable (1'b1),
 
                                .rx_pll_enable (1'b1),
 
                                .rx_readclock (1'b0),
 
                                .rx_readclock (1'b0),
 
                                .rx_reset (1'b0),
 
 
 
                                .rx_syncclock (1'b0));
 
                                .rx_syncclock (1'b0));
 
        defparam
 
        defparam
 
                ALTLVDS_RX_component.buffer_implementation = "RAM",
 
                ALTLVDS_RX_component.buffer_implementation = "RAM",
 
                ALTLVDS_RX_component.cds_mode = "UNUSED",
 
                ALTLVDS_RX_component.cds_mode = "UNUSED",
 
                ALTLVDS_RX_component.common_rx_tx_pll = "ON",
 
                ALTLVDS_RX_component.common_rx_tx_pll = "OFF",
 
                ALTLVDS_RX_component.data_align_rollover = 10,
 
                ALTLVDS_RX_component.data_align_rollover = 10,
 
                ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
 
                ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
 
                ALTLVDS_RX_component.deserialization_factor = 10,
 
                ALTLVDS_RX_component.deserialization_factor = 10,
 
                ALTLVDS_RX_component.dpa_initial_phase_value = 0,
 
                ALTLVDS_RX_component.dpa_initial_phase_value = 0,
 
                ALTLVDS_RX_component.dpll_lock_count = 0,
 
                ALTLVDS_RX_component.dpll_lock_count = 0,
Line 174... Line 176... 
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
 
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
 
// Retrieval info: PRIVATE: PLL_Freq STRING "125.000000"
 
// Retrieval info: PRIVATE: PLL_Freq STRING "125.000000"
 
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
 
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
 
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
 
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
 
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
 
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "Dual-Regional clock"
 
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "Dual-Regional clock"
 
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "1"
 
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Rawperror NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Rawperror NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "0"
 
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "0"
 
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
 
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
 
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
 
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
 
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
 
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
 
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
 
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
 
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
 
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
 
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
 
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
 
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
 
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
 
// Retrieval info: CONSTANT: DPA_INITIAL_PHASE_VALUE NUMERIC "0"
 
// Retrieval info: CONSTANT: DPA_INITIAL_PHASE_VALUE NUMERIC "0"
Line 229... Line 231... 
// Retrieval info: CONSTANT: USE_CORECLOCK_INPUT STRING "OFF"
 
// Retrieval info: CONSTANT: USE_CORECLOCK_INPUT STRING "OFF"
 
// Retrieval info: CONSTANT: USE_DPLL_RAWPERROR STRING "OFF"
 
// Retrieval info: CONSTANT: USE_DPLL_RAWPERROR STRING "OFF"
 
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
 
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
 
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
 
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
 
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "ON"
 
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "ON"
 
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
 
// Retrieval info: USED_PORT: rx_cda_reset 0 0 1 0 INPUT NODEFVAL "rx_cda_reset[0..0]"
 
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
 
// Retrieval info: CONNECT: @rx_cda_reset 0 0 1 0 rx_cda_reset 0 0 1 0
 
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
 
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
 
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
 
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
 
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
 
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
 
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
 
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
 
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL "rx_in[0..0]"
 
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL "rx_in[0..0]"
Line 245... Line 247... 
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
 
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
 
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL "rx_out[9..0]"
 
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL "rx_out[9..0]"
 
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
 
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
 
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL "rx_outclock"
 
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL "rx_outclock"
 
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
 
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
 
 
 
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT NODEFVAL "rx_reset[0..0]"
 
 
 
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.v TRUE FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.v TRUE FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.qip TRUE FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.qip TRUE FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.bsf FALSE TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.bsf FALSE TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx_inst.v FALSE TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx_inst.v FALSE TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx_bb.v FALSE TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx_bb.v FALSE TRUE

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