| Line 45... |
Line 45... |
reg r_TxER_D;
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reg r_TxER_D;
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reg r_Active;
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reg r_Active;
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wire w_TxSop;
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wire w_TxSop;
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wire w_TxEop;
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wire w_TxEop;
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assign w_TxActive = i_TxEN & i_TxER;
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assign w_TxActive = i_TxEN | i_TxER;
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assign w_TxSop = (~r_TxActive && w_TxActive);
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assign w_TxSop = (~r_TxActive & w_TxActive);
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assign w_TxEop = (r_TxActive && ~w_TxActive);
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assign w_TxEop = (r_TxActive & ~w_TxActive);
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always@(posedge i_TxClk)
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always@(posedge i_TxClk)
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begin
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begin
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r_TxActive <= w_TxActive;
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r_TxActive <= w_TxActive;
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| Line 59... |
Line 59... |
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if(w_TxActive) begin
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if(w_TxActive) begin
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if(r_HighNib) r8_Byte <= {i8_TxD[3:0],r4_LowNib};
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if(r_HighNib) r8_Byte <= {i8_TxD[3:0],r4_LowNib};
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if(r_HighNib && (~w_TxSop)) r_TxEN_D <= i_TxEN;
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if(r_HighNib && (~w_TxSop)) r_TxEN_D <= i_TxEN;
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if(r_HighNib && (~w_TxSop)) r_TxER_D <= i_TxER;
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if(r_HighNib && (~w_TxSop)) r_TxER_D <= i_TxER;
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end else
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end else if(r_HighNib)
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begin
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begin
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r_TxEN_D <= 1'b0;
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r_TxEN_D <= 1'b0;
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r_TxER_D <= 1'b0;
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r_TxER_D <= 1'b0;
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end
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end
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if((~r_HighNib)|| (w_TxSop))
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if((~r_HighNib)|| (w_TxSop))
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| Line 102... |
Line 102... |
always@(posedge i_GClk)
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always@(posedge i_GClk)
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begin
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begin
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r_RxActive <= w_RxActive;
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r_RxActive <= w_RxActive;
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if(w_RxSop) r4_Cntr<=4'h0;
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if(w_RxSop) r4_Cntr<=4'h0;
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else if(w_RxActive) r4_Cntr <= ((r4_Cntr==4'h9)?4'h0:(r4_Cntr+4'h1));
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else if(w_RxActive) r4_Cntr <= ((r4_Cntr==4'h9)?4'h0:(r4_Cntr+4'h1));
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else r4_Cntr <= 4'h0;
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if(r4_Cntr==4'h0) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[3:0]};
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if(r4_Cntr==4'h0) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[3:0]};
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else if(r4_Cntr==4'h5) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[7:4]};
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else if(r4_Cntr==4'h5) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[7:4]};
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end
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end
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always@(posedge i_RxClk)
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always@(posedge i_RxClk)
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