| Line 59... |
Line 59... |
stRX_CB = 21'h000004,
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stRX_CB = 21'h000004,
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stRX_CC = 21'h000008,
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stRX_CC = 21'h000008,
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stRX_CD = 21'h000010,
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stRX_CD = 21'h000010,
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stRX_INVALID = 21'h000020,
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stRX_INVALID = 21'h000020,
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stIDLE_D = 21'h000040,
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stIDLE_D = 21'h000040,
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stCARRIER_DTEC = 21'h000080,
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stFALSE_CARRIER = 21'h000080,
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stFALSE_CARRIER = 21'h000100,
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stSTART_OF_PKT = 21'h000100,
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stSTART_OF_PKT = 21'h000200,
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stEARLY_END = 21'h000200,
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stRECEIVE = 21'h000400,
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stTRI_RRI = 21'h000400,
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stEARLY_END = 21'h000800,
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stTRR_EXTEND = 21'h000800,
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stTRI_RRI = 21'h001000,
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stPKT_BURST_RRS = 21'h001000,
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stTRR_EXTEND = 21'h002000,
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stRX_DATA_ERR = 21'h002000,
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stEPD2_CHK_END = 21'h004000,
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stRX_DATA = 21'h004000,
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stPKT_BURST_RRS = 21'h008000,
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stEARLY_END_EXT = 21'h008000,
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stRX_DATA_ERR = 21'h010000,
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stEXT_ERROR = 21'h010000;
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stRX_DATA = 21'h020000,
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stEARLY_END_EXT = 21'h040000,
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stEXT_ERROR = 21'h080000,
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stLINK_FAILED = 21'h100000;
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reg [20:00] r21_State;
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reg [20:00] r21_NxtState;
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reg [16:00] r17_State;
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reg [16:00] r21_NxtState;
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wire wSUDIK28_5;
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wire wSUDIK28_5;
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wire wSUDID21_5;
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wire wSUDID21_5;
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wire wSUDID2_2;
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wire wSUDID2_2;
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wire wCarrierDtect;//what is this
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wire wCarrierDtect;//what is this
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| Line 96... |
Line 95... |
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//synthesis translate_off
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//synthesis translate_off
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reg [8*30-1:0] rvStateName;
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reg [8*30-1:0] rvStateName;
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always@(*)
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always@(*)
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begin
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begin
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case(r21_State)
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case(r17_State)
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stWAIT_FOR_K : rvStateName <= "Wait For K";
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stWAIT_FOR_K : rvStateName <= "Wait For K";
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stRX_K : rvStateName <= "RX K";
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stRX_K : rvStateName <= "RX K";
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stRX_CB : rvStateName <= "RX CB";
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stRX_CB : rvStateName <= "RX CB";
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stRX_CC : rvStateName <= "RX CC";
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stRX_CC : rvStateName <= "RX CC";
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stRX_CD : rvStateName <= "RX CD";
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stRX_CD : rvStateName <= "RX CD";
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stRX_INVALID : rvStateName <= "RX Invalid";
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stRX_INVALID : rvStateName <= "RX Invalid";
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stIDLE_D : rvStateName <= "IDLE D";
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stIDLE_D : rvStateName <= "IDLE D";
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stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
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//stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
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stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
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stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
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stSTART_OF_PKT : rvStateName <= "Start of Packet";
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stSTART_OF_PKT : rvStateName <= "Start of Packet";
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stRECEIVE : rvStateName <= "Receiving";
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//stRECEIVE : rvStateName <= "Receiving";
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stEARLY_END : rvStateName <= "Early End";
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stEARLY_END : rvStateName <= "Early End";
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stTRI_RRI : rvStateName <= "TRI RRI";
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stTRI_RRI : rvStateName <= "TRI RRI";
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stTRR_EXTEND : rvStateName <= "TRR Extend";
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stTRR_EXTEND : rvStateName <= "TRR Extend";
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stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
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//stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
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stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
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stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
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stRX_DATA_ERR : rvStateName <= "RX DATA Error";
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stRX_DATA_ERR : rvStateName <= "RX DATA Error";
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stRX_DATA : rvStateName <= "RX DATA";
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stRX_DATA : rvStateName <= "RX DATA";
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stEARLY_END_EXT : rvStateName <= "Early End Ext";
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stEARLY_END_EXT : rvStateName <= "Early End Ext";
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stEXT_ERROR : rvStateName <= "Ext Error";
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stEXT_ERROR : rvStateName <= "Ext Error";
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stLINK_FAILED : rvStateName <= "Link Failed";
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//stLINK_FAILED : rvStateName <= "Link Failed";
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endcase
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endcase
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//$display("mReceive State: %s",rvStateName);
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//$display("mReceive State: %s",rvStateName);
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end
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end
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//synthesis translate_on
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//synthesis translate_on
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| Line 130... |
Line 129... |
assign wSUDI = ~i_RxCodeInvalid;
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assign wSUDI = ~i_RxCodeInvalid;
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assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
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assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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r21_State <= stWAIT_FOR_K;
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r17_State <= stWAIT_FOR_K;
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end else begin
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end else begin
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r21_State <= r21_NxtState;
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r17_State <= r21_NxtState;
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end
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end
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assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
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assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
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assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
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assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
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assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
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assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
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always@(*)
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always@(*)
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begin
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begin
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case(r21_State)
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case(r17_State)
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stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
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stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
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stRX_K : if(wSUDID21_5||wSUDID2_2)
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stRX_K : if(wSUDID21_5||wSUDID2_2)
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r21_NxtState <= stRX_CB; else
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r21_NxtState <= stRX_CB; else
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if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
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if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
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r21_NxtState <= stRX_INVALID; else
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r21_NxtState <= stRX_INVALID; else
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| Line 238... |
Line 237... |
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
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r21_NxtState <= stEXT_ERROR;
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r21_NxtState <= stEXT_ERROR;
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endcase
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endcase
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end
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end
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assign o_RUDIConfig = (r21_State==stRX_CD )?1'b1:1'b0;
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assign o_RUDIConfig = (r17_State==stRX_CD )?1'b1:1'b0;
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assign o_RUDIIdle = (r21_State==stIDLE_D )?1'b1:1'b0;
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assign o_RUDIIdle = (r17_State==stIDLE_D )?1'b1:1'b0;
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assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
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assign o_RUDIInvalid= (r17_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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o_Receiving <= 1'b0;
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o_Receiving <= 1'b0;
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o_RxDV <= 1'b0;
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o_RxDV <= 1'b0;
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| Line 306... |
Line 305... |
stEARLY_END_EXT : o_RxER <= 1'b1;
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stEARLY_END_EXT : o_RxER <= 1'b1;
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stEXT_ERROR : begin
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stEXT_ERROR : begin
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o_RxDV <= 1'b0;
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o_RxDV <= 1'b0;
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o8_RxD <= 8'b0001_1111;
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o8_RxD <= 8'b0001_1111;
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end
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end
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stLINK_FAILED : begin
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// stLINK_FAILED : begin
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if(o_Receiving==1'b1)
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// if(o_Receiving==1'b1)
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begin
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// begin
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o_Receiving <= 1'b0;
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// o_Receiving <= 1'b0;
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o_RxER <= 1'b1;
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// o_RxER <= 1'b1;
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end else
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// end else
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begin
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// begin
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o_RxDV <= 1'b0;
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// o_RxDV <= 1'b0;
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o_RxER <= 1'b0;
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// o_RxER <= 1'b0;
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end
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// end
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if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
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// if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
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end
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// end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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