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/*
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/*
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Developed By Jeff Lieu (lieumychuong@gmail.com)
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Copyright � 2012 JeffLieu-lieumychuong@gmail.com
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This file is part of SGMII-IP-Core.
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SGMII-IP-Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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SGMII-IP-Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
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File :
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File :
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Description :
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Description :
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This core implements:
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This core implements:
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B1000-X Standard
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B1000-X Standard
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PCS/PMA of SGMII MAC Side
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PCS/PMA of SGMII MAC Side
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wire w_TxForceNegDisp;
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wire w_TxForceNegDisp;
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wire w_PllLocked;
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wire w_PllLocked;
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wire [20:00] w21_LinkTimer;
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wire [20:00] w21_LinkTimer;
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wire w_TxEN,w_TxER,w_RxER, w_RxDV;
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wire w_TxEN,w_TxER,w_RxER, w_RxDV;
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wire [07:00] w8_RxD, w8_TxD;
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wire [07:00] w8_RxD, w8_TxD;
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wire w_BitSlip;
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wire w_Invalid;//Not Used
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wire w_TxEven;//Not Used
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wire w_CurrentParity;
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//MII Clock Gen
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//MII Clock Gen
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reg [6:0] r7_Cntr;
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reg [6:0] r7_Cntr;
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reg r_MIIClk;
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reg r_MIIClk;
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reg r_MIIClk_D;
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reg r_MIIClk_D;
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.i8_RxD (w8_RxD));
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.i8_RxD (w8_RxD));
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generate
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generate
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genvar STAGE;
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genvar STAGE;
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for(STAGE=0;STAGE<3;STAGE=STAGE+1)
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for(STAGE=0;STAGE<3;STAGE=STAGE+1)
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begin
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begin:PreCheck
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assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
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assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
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assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
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assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
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assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
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assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
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assign w3_PreCheckIsD21_5[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
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assign w3_PreCheckIsD21_5[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
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assign w3_PreCheckIsD2_2[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
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assign w3_PreCheckIsD2_2[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
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.i_WEn (i_WEn),
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.i_WEn (i_WEn),
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.i8_Addr (iv_Addr),
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.i8_Addr (iv_Addr),
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.i32_WrData (i32_WrData),
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.i32_WrData (i32_WrData),
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.o32_RdData (o32_RdData),
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.o32_RdData (o32_RdData),
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.o_Ack (o_Ack),
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.o_Ack (o_Ack),
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.o_Stall (o_Stall),
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.o_Stall (),
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.io_Mdio (io_Mdio),
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.io_Mdio (io_Mdio),
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.i_Mdc (i_Mdc),
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.i_Mdc (i_Mdc),
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//Register in and out,
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//Register in and out,
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.o_RUDIInvalid (w_RUDIInvalid),
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.o_RUDIInvalid (w_RUDIInvalid),
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.o_RxDV (w_RxDV ),
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.o_RxDV (w_RxDV ),
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.o_RxER (w_RxER ),
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.o_RxER (w_RxER ),
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.o8_RxD (w8_RxD ),
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.o8_RxD (w8_RxD ),
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.o_Invalid (o_Invalid),
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.o_Invalid (w_Invalid),
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.o_Receiving (w_Receiving),
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.o_Receiving (w_Receiving),
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.i_Clk (w_ClkSys),
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.i_Clk (w_ClkSys),
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.i_ARst_L (w_ARstLogic_L));
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.i_ARst_L (w_ARstLogic_L));
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mANCtrl u0ANCtrl(
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mANCtrl u0ANCtrl(
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.o_SerTx (o_SerTx ),
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.o_SerTx (o_SerTx ),
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.i_RefClk125M (i_RefClk125M ),
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.i_RefClk125M (i_RefClk125M ),
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.o_CoreClk (w_ClkSys ),
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.o_CoreClk (w_ClkSys ),
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.i_GxBPwrDwn (w_GxBPowerDown ),
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.i_GxBPwrDwn (w_GxBPowerDown ),
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.i_XcverDigitalRst (~w_ARstLogic_L ),
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.i_XcverDigitalRst (~i_ARstHardware_L ),
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.o_PllLocked (w_PllLocked ),
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.o_PllLocked (w_PllLocked ),
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.i_RxBitSlip (w_BitSlip ),
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.i_RxBitSlip (w_BitSlip ),
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.o_SignalDetect (),
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.o_SignalDetect (),
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.o8_RxCodeGroup (w8_RxCode ),
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.o8_RxCodeGroup (w8_RxCode ),
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.o_RxCodeCtrl (w_RxCodeCtrl ),
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.o_RxCodeCtrl (w_RxCodeCtrl ),
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.i8_TxCodeGroup (w8_TxCode ),
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.i8_TxCodeGroup (w8_TxCode ),
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.i_TxCodeValid (w_TxCodeValid ),
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.i_TxCodeValid (w_TxCodeValid ),
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.i_TxCodeCtrl (w_TxCodeCtrl ),
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.i_TxCodeCtrl (w_TxCodeCtrl ),
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.i_TxForceNegDisp (w_TxForceNegDisp ),
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.i_TxForceNegDisp (1'b0 ),
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.o_RunningDisparity (w_CurrentParity));
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.o_RunningDisparity (w_CurrentParity));
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assign o_GMIIClk = w_ClkSys;
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assign o_GMIIClk = w_ClkSys;
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always@(posedge w_ClkSys or negedge i_ARstHardware_L )
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always@(posedge w_ClkSys or negedge i_ARstHardware_L )
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