| Line 53... |
Line 53... |
localparam stTX_EOP_EXT= 24'h010000; //End of packet with extension
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localparam stTX_EOP_EXT= 24'h010000; //End of packet with extension
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localparam stTX_EXT_1 = 24'h020000; //Extend 1 cycle to align the COMMA to Even Code group
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localparam stTX_EXT_1 = 24'h020000; //Extend 1 cycle to align the COMMA to Even Code group
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localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
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localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
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localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
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localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
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localparam stCARR_EXT = 24'h100000; //Carrier extension
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localparam stCARR_EXT = 24'h100000; //Carrier extension
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localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
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//localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
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localparam stSTART_ERR = 24'h400000; //Repeater's state
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localparam stSTART_ERR = 24'h200000; //Repeater's state
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localparam stTX_ERR = 24'h800000; //Repeater's state
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localparam stTX_ERR = 24'h400000; //Repeater's state
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reg [23:00] r24_State;
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reg [22:00] r13_State;
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reg [23:00] w24_NxtState;
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reg [22:00] w24_NxtState;
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wire w_XmitChange;
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wire w_XmitChange;
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reg [02:00] r3_LstXmit;
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reg [02:00] r3_LstXmit;
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reg r_TxEven;
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reg r_TxEven;
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| Line 73... |
Line 73... |
wire w_FifoTxEn;
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wire w_FifoTxEn;
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wire w_FifoTxEr;
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wire w_FifoTxEr;
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wire [07:00] w8_FifoData;
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wire [07:00] w8_FifoData;
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wire w_UpdateXmitChange;
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wire w_UpdateXmitChange;
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wire w_ResetState;
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wire w_ResetState;
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wire r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
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reg r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
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wire w_Disparity;
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wire w_Disparity;
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wire [09:00] w10_FifoDin;
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wire [09:00] w10_FifoDin;
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wire [09:00] w10_FifoQ;
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wire [09:00] w10_FifoQ;
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wire w_FifoRd,w_FifoEmpty;
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wire w_FifoRd,w_FifoEmpty;
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reg [07:00] r8_TxData;
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reg [07:00] r8_TxData;
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assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
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assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
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assign w_TxOSIndicate = (r24_State==stCONFIG_C1A||r24_State==stCONFIG_C1B||r24_State==stCONFIG_C1C||
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assign w_TxOSIndicate = (r13_State==stCONFIG_C1A||r13_State==stCONFIG_C1B||r13_State==stCONFIG_C1C||
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r24_State==stCONFIG_C2A||r24_State==stCONFIG_C2B||r24_State==stCONFIG_C2C||
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r13_State==stCONFIG_C2A||r13_State==stCONFIG_C2B||r13_State==stCONFIG_C2C||
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r24_State==stTX_IDLE||r24_State==stTX_DATA)?1'b0:1'b1;
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r13_State==stTX_IDLE||r13_State==stTX_DATA)?1'b0:1'b1;
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//assign w_UpdateXmitChange =
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//assign w_UpdateXmitChange =
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//FIFO
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//FIFO
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assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
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assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
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assign w_FifoTxEn = w10_FifoQ[9] & (~w_FifoEmpty);
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assign w_FifoTxEn = w10_FifoQ[9] & (~w_FifoEmpty);
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assign w_FifoTxEr = w10_FifoQ[8] & (~w_FifoEmpty);
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assign w_FifoTxEr = w10_FifoQ[8] & (~w_FifoEmpty);
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| Line 100... |
Line 100... |
.o_Full(),
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.o_Full(),
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.ov_Q(w10_FifoQ),
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.ov_Q(w10_FifoQ),
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.i_Clk(i_Clk),
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.i_Clk(i_Clk),
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.i_ARst_L(i_ARst_L));
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.i_ARst_L(i_ARst_L));
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//END FIFO
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//END FIFO
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assign w_FifoRd = ((w_FifoTxEn && (r24_State==stXMIT_DATA||r24_State==stTX_IDLE)))?1'b0:1'b1;
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assign w_FifoRd = ((w_FifoTxEn && (r13_State==stXMIT_DATA||r13_State==stTX_IDLE)))?1'b0:1'b1;
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always@(posedge i_Clk or negedge i_ARst_L)
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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if(i_ARst_L==1'b0) begin
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r24_State <= stTX_TEST;
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r13_State <= stTX_TEST;
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r3_LstXmit <= 3'b000;
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r3_LstXmit <= `cXmitIDLE;
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r_TxEven <= 1'b0;
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r_TxEven <= 1'b0;
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o_TxEven <= 1'b1;
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end
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end
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else
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else
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begin
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begin
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if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
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if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
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r24_State <= w24_NxtState;
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if(w_ResetState)
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r13_State <= stTX_TEST;
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else
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r13_State <= w24_NxtState;
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r_TxEven <= ~r_TxEven;
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r_TxEven <= ~r_TxEven;
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o_TxEven <= r_TxEven;
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o_TxEven <= r_TxEven;
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end
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end
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// always@(posedge i_Clk or posedge w_ResetState)
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// if(w_ResetState)
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// r13_State <= stTX_TEST;
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// else
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// r13_State <= w24_NxtState;
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assign w_UpdateXmitChange = w_ResetState;
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assign w_UpdateXmitChange = w_ResetState;
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assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (r_TxEven==1'b0) && w_TxOSIndicate);
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assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (o_TxEven==1'b0) && w_TxOSIndicate);
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assign w_Disparity = i_CurrentParity;
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assign w_Disparity = i_CurrentParity;
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always@(*)
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always@(*)
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begin
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begin
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if(w_ResetState)
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r24_State <= stTX_TEST;
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// else
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case(r24_State)
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case(r13_State)
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stTX_TEST : if(i3_Xmit==`cXmitCONFIG && r_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
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stTX_TEST : if(i3_Xmit==`cXmitCONFIG && o_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
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if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if((i3_Xmit==`cXmitIDLE &&(~o_TxEven)) || ((~o_TxEven) && i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
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if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
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else w24_NxtState <= stTX_TEST;
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else w24_NxtState <= stTX_TEST;
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stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
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stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
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stCONFIG_C1B : w24_NxtState <= stCONFIG_C1C;
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stCONFIG_C1B : w24_NxtState <= stCONFIG_C1C;
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stCONFIG_C1C : w24_NxtState <= stCONFIG_C1D;
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stCONFIG_C1C : w24_NxtState <= stCONFIG_C1D;
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| Line 217... |
Line 228... |
stCONFIG_C2C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
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stCONFIG_C2C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
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stCONFIG_C2D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
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stCONFIG_C2D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
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stTX_IDLE : begin
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stTX_IDLE : begin
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o8_TxCodeGroupOut <= `K28_5;
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o8_TxCodeGroupOut <= `K28_5;
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o_TxCodeCtrl <= 1'b1;
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o_TxCodeCtrl <= 1'b1;
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r_ToTxData <= 1'b0;
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end
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end
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stIDLE_DATA : begin
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stIDLE_DATA : begin
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o8_TxCodeGroupOut <= (w_Disparity==1'b0)?`D5_6:`D16_2;//Disparity = 0 means positive
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o8_TxCodeGroupOut <= (w_Disparity==1'b1)?`D5_6:`D16_2;//Disparity = 1 means positive
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o_TxCodeCtrl <= 1'b0;
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o_TxCodeCtrl <= 1'b0;
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end
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end
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stXMIT_DATA : begin
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stXMIT_DATA : begin
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o8_TxCodeGroupOut <= `K28_5;
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o8_TxCodeGroupOut <= `K28_5;
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o_TxCodeCtrl <= 1'b1;
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o_TxCodeCtrl <= 1'b1;
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r_ToTxData <= 1'b1;
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end
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end
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stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
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stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
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begin
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begin
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o8_TxCodeGroupOut <= `K30_7;
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o8_TxCodeGroupOut <= `K30_7;
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o_TxCodeCtrl <= 1'b1;
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o_TxCodeCtrl <= 1'b1;
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| Line 302... |
Line 315... |
end
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end
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//synthesis translate_off
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//synthesis translate_off
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reg [239:0] r240_TxStateName;
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reg [239:0] r240_TxStateName;
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always@(*)
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always@(*)
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case(r24_State)
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case(r13_State)
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stTX_TEST : r240_TxStateName<="stTX_TEST ";
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stTX_TEST : r240_TxStateName<="stTX_TEST ";
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stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
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stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
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stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
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stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
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stCONFIG_C1C : r240_TxStateName<="stCONFIG_C1C";
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stCONFIG_C1C : r240_TxStateName<="stCONFIG_C1C";
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stCONFIG_C1D : r240_TxStateName<="stCONFIG_C1D";
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stCONFIG_C1D : r240_TxStateName<="stCONFIG_C1D";
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| Line 324... |
Line 337... |
stTX_EOP_EXT : r240_TxStateName<="stTX_EOP_EXT";
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stTX_EOP_EXT : r240_TxStateName<="stTX_EOP_EXT";
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stTX_EXT_1 : r240_TxStateName<="stTX_EXT_1 ";
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stTX_EXT_1 : r240_TxStateName<="stTX_EXT_1 ";
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stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
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stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
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stEPD3 : r240_TxStateName<="stEPD3 ";
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stEPD3 : r240_TxStateName<="stEPD3 ";
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stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
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stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
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stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
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//stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
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stSTART_ERR : r240_TxStateName<="stSTART_ERR";
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stSTART_ERR : r240_TxStateName<="stSTART_ERR";
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stTX_ERR : r240_TxStateName<="stTX_ERR ";
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stTX_ERR : r240_TxStateName<="stTX_ERR ";
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endcase
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endcase
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//synthesis translate_on
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//synthesis translate_on
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endmodule
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endmodule
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