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generate
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generate
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if(pXcverName=="AltCycIV")
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if(pXcverName=="AltCycIV")
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begin:AltCycIVXcver
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wire [04:00] w5_ReconfigFromGxb;
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wire [04:00] w5_ReconfigFromGxb;
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wire [03:00] w4_ReconfigToGxb;
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wire [03:00] w4_ReconfigToGxb;
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wire w_Reconfiguring;
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wire w_Reconfiguring;
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begin:AltCycIVXcver
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mAltGX u0AltGX (
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mAltGX u0AltGX (
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.cal_blk_clk (i_CalClk),
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.cal_blk_clk (i_CalClk),
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.gxb_powerdown (i_GxBPwrDwn),
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.gxb_powerdown (i_GxBPwrDwn),
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.pll_inclk (i_RefClk125M),
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.pll_inclk (i_RefClk125M),
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.reconfig_clk (i_CalClk),
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.reconfig_clk (i_CalClk),
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.reconfig_togxb (w4_ReconfigToGxb));
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.reconfig_togxb (w4_ReconfigToGxb));
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end
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end
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endgenerate
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endgenerate
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generate
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if(pXcverName=="AltArriaV")
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begin:AltArriaVXcver
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wire [091:00] w92_ReconfigFromGxb;
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wire [139:00] w140_ReconfigToGxb;
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wire w_Reconfiguring;
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mAltAvgxXcver uAltXCver(
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.phy_mgmt_clk (i_RefClk125M), // phy_mgmt_clk.clk
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.phy_mgmt_clk_reset (1'b0), // phy_mgmt_clk_reset.reset
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.phy_mgmt_address (8'h0), // phy_mgmt.address
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.phy_mgmt_read (1'b0), // .read
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.phy_mgmt_readdata (), // .readdata
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.phy_mgmt_waitrequest (), // .waitrequest
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.phy_mgmt_write (1'b0), // .write
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.phy_mgmt_writedata (32'h0), // .writedata
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.tx_ready (), // tx_ready.export
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.rx_ready (), // rx_ready.export
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.pll_ref_clk (i_RefClk125M), // pll_ref_clk.clk
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.tx_serial_data (o_SerTx), // tx_serial_data.export
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.pll_locked (o_PllLocked), // pll_locked.export
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.rx_serial_data (i_SerRx), // rx_serial_data.export
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.rx_runningdisp (o_RunningDisparity), // rx_runningdisp.export
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.rx_patterndetect (w_PatternDtec), // rx_patterndetect.export
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.rx_disperr (w_DispErr), // rx_disperr.export
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.rx_errdetect (w_ErrDtec), // rx_errdetect.export
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.rx_syncstatus (w_SyncStatus), // rx_syncstatus.export
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.tx_clkout (o_TxClk), // tx_clkout.export
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.rx_clkout (), // rx_clkout.export
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.tx_parallel_data (i8_TxCodeGroup), // tx_parallel_data.export
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.tx_datak (i_TxCodeCtrl), // tx_datak.export
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.rx_parallel_data (o8_RxCodeGroup), // rx_parallel_data.export
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.rx_datak (o_RxCodeCtrl), // rx_datak.export
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.reconfig_from_xcvr (w92_ReconfigFromGxb), // reconfig_from_xcvr.reconfig_from_xcvr
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.reconfig_to_xcvr (w140_ReconfigToGxb) // reconfig_to_xcvr.reconfig_to_xcvr
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);
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assign o_SignalDetect = ~(w_ErrDtec|w_DispErr);
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assign o_RxCodeInvalid = w_ErrDtec;
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mAltAvgxReconfig uReconfig(
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.reconfig_busy (w_Reconfiguring), // reconfig_busy.reconfig_busy
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.mgmt_clk_clk (i_CalClk), // mgmt_clk_clk.clk
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.mgmt_rst_reset (i_XcverDigitalRst), // mgmt_rst_reset.reset
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.reconfig_mgmt_address (8'h0), // reconfig_mgmt.address
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.reconfig_mgmt_read (1'b0), // .read
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.reconfig_mgmt_readdata (), // .readdata
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.reconfig_mgmt_waitrequest (), // .waitrequest
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.reconfig_mgmt_write (1'b0), // .write
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.reconfig_mgmt_writedata (32'h0), // .writedata
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.reconfig_to_xcvr (w140_ReconfigToGxb),// reconfig_to_xcvr.reconfig_to_xcvr
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.reconfig_from_xcvr (w92_ReconfigFromGxb)// reconfig_from_xcvr.reconfig_from_xcvr
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);
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end
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endgenerate
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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