| Line 66... |
Line 66... |
-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
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-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
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-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed.
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-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed.
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-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
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-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
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-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
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-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
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-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block, added lookahead register feedback.
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-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block, added lookahead register feedback.
|
|
-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'.
|
--
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--
|
--
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--
|
-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 87... |
Line 88... |
-- start/end commands
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-- start/end commands
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start_i : in std_logic := 'U'; -- reset the engine and start a new hash
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start_i : in std_logic := 'U'; -- reset the engine and start a new hash
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end_i : in std_logic := 'U'; -- marks end of last block data input
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end_i : in std_logic := 'U'; -- marks end of last block data input
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-- handshake
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-- handshake
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di_req_o : out std_logic; -- requests data input for next word
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di_req_o : out std_logic; -- requests data input for next word
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di_ack_i : in std_logic := 'U'; -- high for di_i valid, low for hold
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di_wr_i : in std_logic := 'U'; -- high for di_i valid, low for hold
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error_o : out std_logic; -- signalizes error. output data is invalid
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error_o : out std_logic; -- signalizes error. output data is invalid
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do_valid_o : out std_logic; -- when high, the output is valid
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do_valid_o : out std_logic; -- when high, the output is valid
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-- 256bit output registers
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-- 256bit output registers
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H0_o : out std_logic_vector (31 downto 0);
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H0_o : out std_logic_vector (31 downto 0);
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H1_o : out std_logic_vector (31 downto 0);
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H1_o : out std_logic_vector (31 downto 0);
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| Line 175... |
Line 176... |
port map(
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port map(
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-- inputs
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-- inputs
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clk_i => clk_i,
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clk_i => clk_i,
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ce_i => ce_i,
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ce_i => ce_i,
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bytes_i => bytes_i,
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bytes_i => bytes_i,
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ack_i => di_ack_i,
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wr_i => di_wr_i,
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start_i => start_i,
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start_i => start_i,
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end_i => end_i,
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end_i => end_i,
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error_i => error_pad,
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error_i => error_pad,
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-- output control signals
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-- output control signals
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bitlen_o => msg_bitlen,
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bitlen_o => msg_bitlen,
|
