| Line 41... |
Line 41... |
-- The setup of all circuit blocks is performed in a single extra clock cycle, besides the 64 steps needed to compute a hash block operation,
|
-- The setup of all circuit blocks is performed in a single extra clock cycle, besides the 64 steps needed to compute a hash block operation,
|
-- resulting in a 65-cycle per block hash computation processor. Heavy pipelining is implemented to suppress control path operations logic steps.
|
-- resulting in a 65-cycle per block hash computation processor. Heavy pipelining is implemented to suppress control path operations logic steps.
|
-- The engine is internally implemented as a 256-bit machine, with all combinational operations performed as a single-cycle operation on each
|
-- The engine is internally implemented as a 256-bit machine, with all combinational operations performed as a single-cycle operation on each
|
-- 64 steps of the hash algorithm. Wide transfers of 256-bit data are also performed as single-cycle operations.
|
-- 64 steps of the hash algorithm. Wide transfers of 256-bit data are also performed as single-cycle operations.
|
--
|
--
|
-- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'ack_i' can be
|
-- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'wr_i' can be
|
-- used as a flow control input to hold the processor to wait for slower data.
|
-- used as a flow control input to hold the processor to wait for slower data.
|
--
|
--
|
-- A hash computation starts with a 'start_i' pulse that resets the processor. A pulse of the 'end_i' signal marks the last input data word. The
|
-- A hash computation starts with a 'start_i' pulse that resets the processor. A pulse of the 'end_i' signal marks the last input data word. The
|
-- core will pad the last block according to the SHA256 rules, and present the results of the hash computation at the output registers, raising the
|
-- core will pad the last block according to the SHA256 rules, and present the results of the hash computation at the output registers, raising the
|
-- 'data_valid' signal to mark the end of the computation. The hash results are available at the 256-bit output port.
|
-- 'data_valid' signal to mark the end of the computation. The hash results are available at the 256-bit output port.
|
| Line 70... |
Line 70... |
--
|
--
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- __ _ _ _ _____________________________________________________________________________________________________
|
-- __ _ _ _ _____________________________________________________________________________________________________
|
-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
|
-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
|
-- ___________________________________________ _________________________________________________________
|
-- ___________________________________________ _________________________________________________________
|
-- ack_i __________/____/ \_____/ \_____________... -- 'ack_i' can hold the core for slow data
|
-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data
|
-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
|
-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
|
-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
|
-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
|
-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
| Line 98... |
Line 98... |
--
|
--
|
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- _____________________________________________________________________________________________________
|
-- _____________________________________________________________________________________________________
|
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
|
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
|
-- ___________________________________________________ _________________________________________________________
|
-- ___________________________________________________ _________________________________________________________
|
-- ack_i ________/__________/ \_____/ \_... -- 'ack_i' can hold the core for slow data
|
-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data
|
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
--
|
--
|
--
|
--
|
-- UPDATE BLOCK (delayed start)
|
-- UPDATE BLOCK (delayed start)
|
| Line 116... |
Line 116... |
--
|
--
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- _______ _ _ ___________________________________________________________________________________________________________
|
-- _______ _ _ ___________________________________________________________________________________________________________
|
-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
|
-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
|
-- __________________________________________________ _____________________________________________
|
-- __________________________________________________ _____________________________________________
|
-- ack_i ________________ _ _ ______/ \_____/ \_... -- 'ack_i' valid on rising edge of 'clk_i'
|
-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i'
|
-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\\\\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\\\\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
--
|
--
|
--
|
--
|
-- END BLOCK (success)
|
-- END BLOCK (success)
|
| Line 139... |
Line 139... |
-- ______
|
-- ______
|
-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
|
-- ___________________________________ __________
|
-- ___________________________________ __________
|
-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
|
-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
|
-- ______________________________________ _________
|
-- ______________________________________ _________
|
-- ack_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'ack_i' can hold the core for slow data
|
-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data
|
-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
|
-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
|
-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
|
-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
|
-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
|
-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
|
-- _____ _____ _____ _____ _____ _____ _____ ____
|
-- _____ _____ _____ _____ _____ _____ _____ ____
|
| Line 184... |
Line 184... |
-- _____
|
-- _____
|
-- end_i ____________/ \_________ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ____________/ \_________ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
|
-- _________________ __________
|
-- _________________ __________
|
-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
|
-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
|
-- ____________________ _________
|
-- ____________________ _________
|
-- ack_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'ack_i' valid on rising edge of 'clk_i'
|
-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i'
|
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
|
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
|
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
|
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
|
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
|
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
|
-- _____ _____ _____ _____ ____
|
-- _____ _____ _____ _____ ____
|
| Line 231... |
Line 231... |
-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
|
-- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed.
|
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
|
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
|
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
|
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
|
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
|
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
|
-- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'.
|
-- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'.
|
|
-- 2016/09/25 v0.01.0220 [JD] changed 'ack_i' name to 'wr_i', and changed semantics to 'data write'.
|
--
|
--
|
-----------------------------------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------------------------------
|
-- TODO
|
-- TODO
|
-- ====
|
-- ====
|
--
|
--
|
| Line 249... |
Line 250... |
-- inputs
|
-- inputs
|
clk_i : in std_logic := 'U'; -- system clock
|
clk_i : in std_logic := 'U'; -- system clock
|
ce_i : in std_logic := 'U'; -- core clock enable
|
ce_i : in std_logic := 'U'; -- core clock enable
|
start_i : in std_logic := 'U'; -- reset the processor and start a new hash
|
start_i : in std_logic := 'U'; -- reset the processor and start a new hash
|
end_i : in std_logic := 'U'; -- marks end of last block data input
|
end_i : in std_logic := 'U'; -- marks end of last block data input
|
ack_i : in std_logic := 'U'; -- input word hold control
|
wr_i : in std_logic := 'U'; -- input word write/hold control
|
bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word
|
bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word
|
error_i : in std_logic := 'U'; -- datapath error input from other modules
|
error_i : in std_logic := 'U'; -- datapath error input from other modules
|
-- output control signals
|
-- output control signals
|
bitlen_o : out std_logic_vector (63 downto 0); -- message bit length
|
bitlen_o : out std_logic_vector (63 downto 0); -- message bit length
|
words_sel_o : out std_logic_vector (1 downto 0); -- bitlen insertion control
|
words_sel_o : out std_logic_vector (1 downto 0); -- bitlen insertion control
|
| Line 333... |
Line 334... |
signal core_ce : std_logic; -- clock enable for hash core logic block
|
signal core_ce : std_logic; -- clock enable for hash core logic block
|
signal oregs_ce : std_logic; -- clock enable for output regs logic block
|
signal oregs_ce : std_logic; -- clock enable for output regs logic block
|
signal bytes_ena : std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block
|
signal bytes_ena : std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block
|
signal one_insert : std_logic; -- insert leading one in the padding
|
signal one_insert : std_logic; -- insert leading one in the padding
|
signal di_req : std_logic; -- data request
|
signal di_req : std_logic; -- data request
|
|
signal di_wr_window : std_logic; -- valid data write window
|
signal data_valid : std_logic; -- operation finished. output data is valid
|
signal data_valid : std_logic; -- operation finished. output data is valid
|
signal core_error : std_logic; -- operation aborted. output data is not valid
|
signal core_error : std_logic; -- operation aborted. output data is not valid
|
|
signal data_input_error : std_logic; -- internal error signal for data write
|
signal out_error : std_logic; -- operation aborted. output data is not valid
|
signal out_error : std_logic; -- operation aborted. output data is not valid
|
|
|
begin
|
begin
|
--=============================================================================================
|
--=============================================================================================
|
-- REGISTER TRANSFER PROCESSES
|
-- REGISTER TRANSFER PROCESSES
|
| Line 350... |
Line 353... |
if clk_i'event and clk_i = '1' then
|
if clk_i'event and clk_i = '1' then
|
if reset = '1' then
|
if reset = '1' then
|
-- all registered values are reset on master clear
|
-- all registered values are reset on master clear
|
hash_control_st_reg <= st_reset;
|
hash_control_st_reg <= st_reset;
|
elsif out_error = '1' then
|
elsif out_error = '1' then
|
|
-- error latch: lock on the error state
|
hash_control_st_reg <= st_error;
|
hash_control_st_reg <= st_error;
|
elsif ce_i = '1' then
|
elsif ce_i = '1' then
|
-- all registered values are held on master clock enable
|
-- all registered values are held on master clock enable
|
hash_control_st_reg <= hash_control_st_next;
|
hash_control_st_reg <= hash_control_st_next;
|
end if;
|
end if;
|
| Line 437... |
Line 441... |
sha_last_blk_next <= sha_last_blk_reg;
|
sha_last_blk_next <= sha_last_blk_reg;
|
padding_next <= padding_reg;
|
padding_next <= padding_reg;
|
-- handshaking
|
-- handshaking
|
sha_init <= '0';
|
sha_init <= '0';
|
core_error <= '0';
|
core_error <= '0';
|
|
di_wr_window <= '0';
|
words_sel <= b"00";
|
words_sel <= b"00";
|
data_valid <= '0';
|
data_valid <= '0';
|
di_req <= '0'; -- data request only during data input
|
di_req <= '0'; -- data request only during data input
|
-- state counter
|
-- state counter
|
st_cnt_clr <= '0'; -- only clear the state counter at the beginning of each block
|
st_cnt_clr <= '0'; -- only clear the state counter at the beginning of each block
|
| Line 462... |
Line 467... |
oregs_ld <= '1'; -- load initial hash values
|
oregs_ld <= '1'; -- load initial hash values
|
oregs_ce <= '1'; -- latch initial hash values into output registers
|
oregs_ce <= '1'; -- latch initial hash values into output registers
|
core_ld <= '1'; -- load initial value into core registers
|
core_ld <= '1'; -- load initial value into core registers
|
core_ce <= '1'; -- latch initial value into core registers
|
core_ce <= '1'; -- latch initial value into core registers
|
st_cnt_clr <= '1'; -- reset state counter
|
st_cnt_clr <= '1'; -- reset state counter
|
|
di_wr_window <= '1'; -- enable data write window
|
-- next state
|
-- next state
|
hash_control_st_next <= st_sha_data_input;
|
hash_control_st_next <= st_sha_data_input;
|
|
|
when st_sha_data_input => -- message data words are clocked into the processor
|
when st_sha_data_input => -- message data words are clocked into the processor
|
-- moore outputs
|
-- moore outputs
|
di_req <= '1'; -- request message data
|
di_req <= '1'; -- request message data
|
|
di_wr_window <= '1'; -- enable data write window
|
sch_ce <= wait_run_ce; -- hold the message scheduler with data hold
|
sch_ce <= wait_run_ce; -- hold the message scheduler with data hold
|
st_cnt_ce <= wait_run_ce; -- hold state count with data hold
|
st_cnt_ce <= wait_run_ce; -- hold state count with data hold
|
core_ce <= wait_run_ce; -- hold processing clock with data hold
|
core_ce <= wait_run_ce; -- hold processing clock with data hold
|
-- next state
|
-- next state
|
if wait_run_ce = '1' then
|
if wait_run_ce = '1' then
|
| Line 609... |
Line 616... |
when others => bits_to_add <= to_unsigned( 0, 6);
|
when others => bits_to_add <= to_unsigned( 0, 6);
|
end case;
|
end case;
|
msg_bit_cnt_next <= msg_bit_cnt_reg + bits_to_add;
|
msg_bit_cnt_next <= msg_bit_cnt_reg + bits_to_add;
|
end process msg_bit_cnt_next_combi_proc;
|
end process msg_bit_cnt_next_combi_proc;
|
|
|
-- data input wait/run: insert wait states during data input for 'ack_i' = '0'
|
-- data input wait/run: insert wait states during data input for 'wr_i' = '0'
|
wait_run_proc: wait_run_ce <= '1' when di_req = '1' and ack_i = '1' else '0';
|
wait_run_proc: wait_run_ce <= '1' when di_req = '1' and wr_i = '1' else '0';
|
|
|
-- padding one-insertion control
|
-- padding one-insertion control
|
one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0';
|
one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0';
|
|
|
-- bit counter clock enable
|
-- bit counter clock enable
|
| Line 622... |
Line 629... |
|
|
-- state counter next logic
|
-- state counter next logic
|
st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1;
|
st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1;
|
|
|
-- bytes_i error logic
|
-- bytes_i error logic
|
bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and ack_i = '1' else bytes_error_reg;
|
bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and wr_i = '1' else bytes_error_reg;
|
|
|
|
-- data input error logic
|
|
data_input_error_proc: data_input_error <= '1' when wr_i = '1' and di_wr_window /= '1' else '0';
|
|
|
-- error detection logic
|
-- error detection logic
|
out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' else '0';
|
out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' or data_input_error = '1' else '0';
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- OUTPUT LOGIC PROCESSES
|
-- OUTPUT LOGIC PROCESSES
|
--=============================================================================================
|
--=============================================================================================
|
|
|
