| Line 52... |
Line 52... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity sha256_regs is
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entity sha256_regs is
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port (
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port (
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clk_i : in std_logic := 'X'; -- system clock
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clk_i : in std_logic := 'U'; -- system clock
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ce_i : in std_logic := 'X'; -- clock enable from control logic
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ce_i : in std_logic := 'U'; -- clock enable from control logic
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ld_i : in std_logic := 'X'; -- internal mux selection from control logic
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ld_i : in std_logic := 'U'; -- internal mux selection from control logic
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A_i : in std_logic_vector (31 downto 0) := (others => 'X');
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A_i : in std_logic_vector (31 downto 0) := (others => 'U');
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B_i : in std_logic_vector (31 downto 0) := (others => 'X');
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B_i : in std_logic_vector (31 downto 0) := (others => 'U');
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C_i : in std_logic_vector (31 downto 0) := (others => 'X');
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C_i : in std_logic_vector (31 downto 0) := (others => 'U');
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D_i : in std_logic_vector (31 downto 0) := (others => 'X');
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D_i : in std_logic_vector (31 downto 0) := (others => 'U');
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E_i : in std_logic_vector (31 downto 0) := (others => 'X');
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E_i : in std_logic_vector (31 downto 0) := (others => 'U');
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F_i : in std_logic_vector (31 downto 0) := (others => 'X');
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F_i : in std_logic_vector (31 downto 0) := (others => 'U');
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G_i : in std_logic_vector (31 downto 0) := (others => 'X');
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G_i : in std_logic_vector (31 downto 0) := (others => 'U');
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H_i : in std_logic_vector (31 downto 0) := (others => 'X');
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H_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K0_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K0_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K1_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K1_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K2_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K2_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K3_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K3_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K4_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K4_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K5_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K5_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K6_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K6_i : in std_logic_vector (31 downto 0) := (others => 'U');
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K7_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K7_i : in std_logic_vector (31 downto 0) := (others => 'U');
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N0_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N0_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N1_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N1_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N2_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N2_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N3_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N3_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N4_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N4_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N5_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N5_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N6_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N6_o : out std_logic_vector (31 downto 0) := (others => 'U');
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N7_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N7_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H0_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H0_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H1_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H1_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H2_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H2_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H3_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H3_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H4_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H4_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H5_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H5_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H6_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H6_o : out std_logic_vector (31 downto 0) := (others => 'U');
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H7_o : out std_logic_vector (31 downto 0) := (others => 'X')
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H7_o : out std_logic_vector (31 downto 0) := (others => 'U')
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);
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);
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end sha256_regs;
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end sha256_regs;
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architecture rtl of sha256_regs is
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architecture rtl of sha256_regs is
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-- output result registers
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-- output result registers
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signal reg_H4 : unsigned (31 downto 0) := (others => '0');
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signal reg_H4 : unsigned (31 downto 0) := (others => '0');
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signal reg_H5 : unsigned (31 downto 0) := (others => '0');
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signal reg_H5 : unsigned (31 downto 0) := (others => '0');
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signal reg_H6 : unsigned (31 downto 0) := (others => '0');
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signal reg_H6 : unsigned (31 downto 0) := (others => '0');
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signal reg_H7 : unsigned (31 downto 0) := (others => '0');
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signal reg_H7 : unsigned (31 downto 0) := (others => '0');
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-- word shifter wires
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-- word shifter wires
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signal next_reg_H0 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H0 : unsigned (31 downto 0);
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signal next_reg_H1 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H1 : unsigned (31 downto 0);
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signal next_reg_H2 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H2 : unsigned (31 downto 0);
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signal next_reg_H3 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H3 : unsigned (31 downto 0);
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signal next_reg_H4 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H4 : unsigned (31 downto 0);
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signal next_reg_H5 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H5 : unsigned (31 downto 0);
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signal next_reg_H6 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H6 : unsigned (31 downto 0);
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signal next_reg_H7 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H7 : unsigned (31 downto 0);
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-- internal modulo adders
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-- internal modulo adders
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signal sum0 : unsigned (31 downto 0) := (others => '0');
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signal sum0 : unsigned (31 downto 0);
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signal sum1 : unsigned (31 downto 0) := (others => '0');
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signal sum1 : unsigned (31 downto 0);
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signal sum2 : unsigned (31 downto 0) := (others => '0');
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signal sum2 : unsigned (31 downto 0);
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signal sum3 : unsigned (31 downto 0) := (others => '0');
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signal sum3 : unsigned (31 downto 0);
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signal sum4 : unsigned (31 downto 0) := (others => '0');
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signal sum4 : unsigned (31 downto 0);
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signal sum5 : unsigned (31 downto 0) := (others => '0');
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signal sum5 : unsigned (31 downto 0);
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signal sum6 : unsigned (31 downto 0) := (others => '0');
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signal sum6 : unsigned (31 downto 0);
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signal sum7 : unsigned (31 downto 0) := (others => '0');
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signal sum7 : unsigned (31 downto 0);
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begin
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begin
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--=============================================================================================
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--=============================================================================================
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-- OUTPUT RESULT REGISTERS LOGIC
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-- OUTPUT RESULT REGISTERS LOGIC
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--=============================================================================================
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--=============================================================================================
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-- The output result registers hold the intermediate values for the hash update blocks, and also the final 256bit hash value.
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-- The output result registers hold the intermediate values for the hash update blocks, and also the final 256bit hash value.
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