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[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [sha256_test.vhd] - Diff between revs 2 and 6

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Rev 2 Rev 6
Line 1... Line 1... 
-----------------------------------------------------------------------------------------------------------------------
 
-----------------------------------------------------------------------------------------------------------------------
 
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
 
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com
 
-- 
-- 
-- Create Date:     09:56:30 05/22/2016  
-- Create Date:     09:56:30 05/22/2016  
-- Module Name:     sha256_test.vhd
 
-- Module Name:     sha256_test.vhd
 
-- Project Name:    sha256 engine
 
-- Project Name:    sha256 engine
 
-- Target Devices:  Spartan-6
 
-- Target Devices:  Spartan-6
Line 159... Line 159... 
--                                                                                                     ___________                 
--                                                                                                     ___________                 
--      do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/           \________________...     -- 'do_valid_o' goes high at the end of a computation
 
--      do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/           \________________...     -- 'do_valid_o' goes high at the end of a computation
 
--
 
--
 
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
 
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
 
--                                                                   
--                                                                   
--      Author(s):      Jonny Doin, jonnydoin@gridvortex.com, jonnydoin@gmail.com
 
--      This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
 
--                                                                   
--                                                                   
--      Copyright (C) 2016 GridVortex, All Rights Reserved
 
--      Author(s):      Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
 
--      --------------------------------------------------
 
--                                                                   
 
 
--      Copyright (C) 2016 Jonny Doin
 
 
 
--      -----------------------------
 
 
 
--                                                                   
 
 
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
 
 
--      removed from the file and that any derivative work contains the original copyright notice and the associated 
 
 
--      disclaimer. 
 
 
--                                                                   
 
 
--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
 
 
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
 
 
--      (at your option) any later version.
 
 
 
--                                                                   
 
 
--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
 
 
 
--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
 
 
--      details.
 
 
 
--
 
 
 
--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
 
 
--      it from http://www.gnu.org/licenses/lgpl.txt
 
--                                                                   
--                                                                   
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
 
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
 
--
 
--
 
-- 2016/05/22   v0.01.0010  [JD]    started development. design of blocks and port interfaces.
 
-- 2016/05/22   v0.01.0010  [JD]    started development. design of blocks and port interfaces.
 
-- 2016/06/05   v0.01.0090  [JD]    all modules integrated. testbench for basic test vectors verification.
 
-- 2016/06/05   v0.01.0090  [JD]    all modules integrated. testbench for basic test vectors verification.
Line 304... Line 321... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"61626300";
 
 
 
        dut_bytes <= b"11";
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
 
 
        dut_di_ack <= '1';
 
        dut_di_ack <= '1';
 
        dut_di <= x"61626300";
 
 
 
        dut_bytes <= b"11";
 
 
 
        dut_end <= '1';
 
        dut_end <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_end <= '0';
 
        dut_end <= '0';
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
Line 411... Line 427... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"61626364";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di_ack <= '1';
 
        wait until pclk'event and pclk = '1';   -- 'begin' pulse minimum width is one clock
 
        wait until pclk'event and pclk = '1';   -- 'begin' pulse minimum width is one clock
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di_ack <= '1';
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di <= x"61626364";
 
 
 
        wait until pclk'event and pclk = '1';
 
 
 
        dut_di <= x"62636465";
 
        dut_di <= x"62636465";
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di <= x"63646566";
 
        dut_di <= x"63646566";
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di <= x"64656667";
 
        dut_di <= x"64656667";
Line 480... Line 495... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"bd000000";
 
 
 
        dut_bytes <= b"01";
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
 
 
        dut_di_ack <= '1';
 
        dut_di_ack <= '1';
 
        dut_di <= x"bd000000";
 
 
 
        dut_bytes <= b"01";
 
 
 
        dut_end <= '1';
 
        dut_end <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_end <= '0';
 
        dut_end <= '0';
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
Line 523... Line 537... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"c98c8e55";
 
 
 
        dut_bytes <= b"00";
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
 
 
        dut_di_ack <= '1';
 
        dut_di_ack <= '1';
 
        dut_di <= x"c98c8e55";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_end <= '1';
 
        dut_end <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_end <= '0';
 
        dut_end <= '0';
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
        if dut_error /= '1' and dut_do_valid /= '1' then
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
 
            while dut_error /= '1' and dut_do_valid /= '1' loop
Line 566... Line 579... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"00000000";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di_ack <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di_ack <= '1';
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di <= x"00000000";
 
 
 
        wait until pclk'event and pclk = '1';
 
 
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
Line 623... Line 635... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"00000000";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di_ack <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di_ack <= '1';
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di <= x"00000000";
 
 
 
        wait until pclk'event and pclk = '1';
 
 
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
Line 679... Line 690... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"00000000";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di_ack <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di_ack <= '1';
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di <= x"00000000";
 
 
 
        wait until pclk'event and pclk = '1';
 
 
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
Line 737... Line 747... 
        dut_end <= '0';
 
        dut_end <= '0';
 
        dut_di_ack <= '0';
 
        dut_di_ack <= '0';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_ce <= '1';
 
        dut_ce <= '1';
 
        dut_start <= '1';
 
        dut_start <= '1';
 
 
 
        dut_di <= x"00000000";
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di_ack <= '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_start <= '0';
 
        dut_start <= '0';
 
        wait until dut_di_req = '1';
 
        wait until dut_di_req = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        dut_di_ack <= '1';
 
 
 
        dut_bytes <= b"00";
 
 
 
        dut_di <= x"00000000";
 
 
 
        wait until pclk'event and pclk = '1';
 
 
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';
 
        wait until pclk'event and pclk = '1';

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