| Line 11... |
Line 11... |
-- Testbench for the GV_SHA256 engine.
|
-- Testbench for the GV_SHA256 engine.
|
-- This is the testbench for the GV_SHA256 engine. It exercises all the input control signals and error generation,
|
-- This is the testbench for the GV_SHA256 engine. It exercises all the input control signals and error generation,
|
-- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the
|
-- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the
|
-- 1 million chars.
|
-- 1 million chars.
|
--
|
--
|
|
-- The logic implements a fast engine, with 66 cycles per 512-bit block.
|
|
--
|
-- The following waveforms describe the operation of the engine control signals for message start, update and end.
|
-- The following waveforms describe the operation of the engine control signals for message start, update and end.
|
--
|
--
|
-- BEGIN BLOCK (1st block)
|
-- BEGIN BLOCK (1st block)
|
-- ======================
|
-- ======================
|
--
|
--
|
| Line 33... |
Line 35... |
--
|
--
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- __ _ _ _ _____________________________________________________________________________________________________
|
-- __ _ _ _ _____________________________________________________________________________________________________
|
-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
|
-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
|
-- ___________________________________________ _________________________________________________________
|
-- ___________________________________________ _________________________________________________________
|
-- ack_i __________/____/ \_____/ \_____________... -- 'ack_i' can hold the core for slow data
|
-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data
|
-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
|
-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
|
-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
|
-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
|
-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
|
| Line 61... |
Line 63... |
--
|
--
|
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- _____________________________________________________________________________________________________
|
-- _____________________________________________________________________________________________________
|
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
|
-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
|
-- ___________________________________________________ _________________________________________________________
|
-- ___________________________________________________ _________________________________________________________
|
-- ack_i ________/__________/ \_____/ \_... -- 'ack_i' can hold the core for slow data
|
-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data
|
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
--
|
--
|
--
|
--
|
-- UPDATE BLOCK (delayed start)
|
-- UPDATE BLOCK (delayed start)
|
| Line 79... |
Line 81... |
--
|
--
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
|
-- _______ _ _ ___________________________________________________________________________________________________________
|
-- _______ _ _ ___________________________________________________________________________________________________________
|
-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
|
-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
|
-- __________________________________________________ _____________________________________________
|
-- __________________________________________________ _____________________________________________
|
-- ack_i ________________ _ _ ______/ \_____/ \_... -- 'ack_i' valid on rising edge of 'clk_i'
|
-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i'
|
-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
|
-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\_____W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\__Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\_____W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\__Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
|
--
|
--
|
--
|
--
|
-- END BLOCK (success)
|
-- END BLOCK (success)
|
| Line 102... |
Line 104... |
-- ______
|
-- ______
|
-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
|
-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
|
-- ___________________________________ __________
|
-- ___________________________________ __________
|
-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
|
-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
|
-- ______________________________________ _________
|
-- ______________________________________ _________
|
-- ack_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'ack_i' can hold the core for slow data
|
-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data
|
-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
|
-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
|
-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
|
-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
|
-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
|
-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
|
-- _____ _____ _____ _____ _____ _____ _____ ____
|
-- _____ _____ _____ _____ _____ _____ _____ ____
|
| Line 147... |
Line 149... |
-- ______
|
-- ______
|
-- end_i ______________/ \______ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
|
-- end_i ______________/ \______ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
|
-- _________________ __________
|
-- _________________ __________
|
-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
|
-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
|
-- ____________________ _________
|
-- ____________________ _________
|
-- ack_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'ack_i' valid on rising edge of 'clk_i'
|
-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i'
|
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
|
-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
|
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
|
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
|
-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
|
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
|
-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
|
-- _____ _____ _____ _____ ____
|
-- _____ _____ _____ _____ ____
|
| Line 192... |
Line 194... |
-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic.
|
-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic.
|
-- 2016/06/07 v0.01.0105 [JD] sha256 verification against all NIST-FIPS-180-4 test vectors passed.
|
-- 2016/06/07 v0.01.0105 [JD] sha256 verification against all NIST-FIPS-180-4 test vectors passed.
|
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
|
-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
|
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
|
-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
|
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
|
-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
|
|
-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'.
|
--
|
--
|
-----------------------------------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------------------------------
|
-- TODO
|
-- TODO
|
-- ====
|
-- ====
|
--
|
--
|
| Line 236... |
Line 239... |
-- start/end commands
|
-- start/end commands
|
signal dut_start : std_logic; -- reset the processor and start a new hash
|
signal dut_start : std_logic; -- reset the processor and start a new hash
|
signal dut_end : std_logic; -- marks end of last block data input
|
signal dut_end : std_logic; -- marks end of last block data input
|
-- handshake
|
-- handshake
|
signal dut_di_req : std_logic; -- requests data input for next word
|
signal dut_di_req : std_logic; -- requests data input for next word
|
signal dut_di_ack : std_logic; -- high for di_i valid, low for hold
|
signal dut_di_wr : std_logic; -- high for di_i write, low for hold
|
signal dut_error : std_logic; -- signalizes error. output data is invalid
|
signal dut_error : std_logic; -- signalizes error. output data is invalid
|
signal dut_do_valid : std_logic; -- when high, the output is valid
|
signal dut_do_valid : std_logic; -- when high, the output is valid
|
-- 256bit output registers
|
-- 256bit output registers
|
signal dut_H0 : std_logic_vector (31 downto 0);
|
signal dut_H0 : std_logic_vector (31 downto 0);
|
signal dut_H1 : std_logic_vector (31 downto 0);
|
signal dut_H1 : std_logic_vector (31 downto 0);
|
| Line 271... |
Line 274... |
-- start/end commands
|
-- start/end commands
|
start_i => dut_start,
|
start_i => dut_start,
|
end_i => dut_end,
|
end_i => dut_end,
|
-- handshake
|
-- handshake
|
di_req_o => dut_di_req,
|
di_req_o => dut_di_req,
|
di_ack_i => dut_di_ack,
|
di_wr_i => dut_di_wr,
|
error_o => dut_error,
|
error_o => dut_error,
|
do_valid_o => dut_do_valid,
|
do_valid_o => dut_do_valid,
|
-- 256bit output registers
|
-- 256bit output registers
|
H0_o => dut_H0,
|
H0_o => dut_H0,
|
H1_o => dut_H1,
|
H1_o => dut_H1,
|
| Line 317... |
Line 320... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"61626300";
|
dut_di <= x"61626300";
|
dut_bytes <= b"11";
|
dut_bytes <= b"11";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
dut_di_ack <= '1';
|
end if;
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 358... |
Line 364... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
wait for 25 ns; -- TEST: stretch 'begin' pulse
|
wait for 25 ns; -- TEST: stretch 'begin' pulse
|
dut_start <= '0';
|
dut_start <= '0';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di_ack <= '1';
|
dut_di_wr <= '1';
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di <= x"61626364";
|
dut_di <= x"61626364";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"62636465";
|
dut_di <= x"62636465";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 382... |
Line 390... |
dut_di <= x"65666768";
|
dut_di <= x"65666768";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"66676869";
|
dut_di <= x"66676869";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"6768696A";
|
dut_di <= x"6768696A";
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di_ack <= '1'; -- TEST: slow inputs with 'ack' handshake
|
dut_di_wr <= '1'; -- TEST: slow inputs with 'ack' handshake
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"68696A6B";
|
dut_di <= x"68696A6B";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"696A6B6C";
|
dut_di <= x"696A6B6C";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 407... |
Line 415... |
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
dut_bytes <= b"01"; -- TEST: change 'bytes' value after END
|
dut_bytes <= b"01"; -- TEST: change 'bytes' value after END
|
wait for 75 ns; -- TEST: stretch 'end' pulse
|
wait for 75 ns; -- TEST: stretch 'end' pulse
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 423... |
Line 432... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"61626364";
|
dut_di <= x"61626364";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di_ack <= '1';
|
|
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"62636465";
|
dut_di <= x"62636465";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"63646566";
|
dut_di <= x"63646566";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 462... |
Line 473... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_di <= x"6E6F7071";
|
dut_di <= x"6E6F7071";
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 491... |
Line 503... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"bd000000";
|
dut_di <= x"bd000000";
|
dut_bytes <= b"01";
|
dut_bytes <= b"01";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
dut_di_ack <= '1';
|
end if;
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 533... |
Line 548... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"c98c8e55";
|
dut_di <= x"c98c8e55";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
dut_di_ack <= '1';
|
end if;
|
|
dut_di_wr <= '1';
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 575... |
Line 594... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di_ack <= '1';
|
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 602... |
Line 623... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '1';
|
dut_end <= '1';
|
dut_bytes <= b"11";
|
dut_bytes <= b"11";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 631... |
Line 653... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di_ack <= '1';
|
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 657... |
Line 681... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 686... |
Line 711... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di_ack <= '1';
|
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 714... |
Line 741... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '1';
|
dut_end <= '1';
|
dut_bytes <= b"01";
|
dut_bytes <= b"01";
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 743... |
Line 771... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di_ack <= '1';
|
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
|
dut_di_wr <= '1';
|
|
if dut_di_req = '0' then
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
end if;
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
| Line 771... |
Line 801... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 800... |
Line 831... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_di_ack <= '1';
|
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := 0;
|
count_blocks := 0;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
loop
|
loop
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 15;
|
exit when words = 15;
|
end loop;
|
end loop;
|
|
dut_di_wr <= '0';
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := count_blocks + 1;
|
count_blocks := count_blocks + 1;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
exit when blocks = 14;
|
exit when blocks = 14;
|
end loop;
|
end loop;
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 8;
|
exit when words = 8;
|
end loop;
|
end loop;
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 868... |
Line 904... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_di_ack <= '1';
|
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di <= x"41414141";
|
dut_di <= x"41414141";
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := 0;
|
count_blocks := 0;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
loop
|
loop
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 15;
|
exit when words = 15;
|
end loop;
|
end loop;
|
|
dut_di_wr <= '0';
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := count_blocks + 1;
|
count_blocks := count_blocks + 1;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
exit when blocks = 14;
|
exit when blocks = 14;
|
end loop;
|
end loop;
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 8;
|
exit when words = 8;
|
end loop;
|
end loop;
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 936... |
Line 977... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_di_ack <= '1';
|
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di <= x"55555555";
|
dut_di <= x"55555555";
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := 0;
|
count_blocks := 0;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
loop
|
loop
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 15;
|
exit when words = 15;
|
end loop;
|
end loop;
|
|
dut_di_wr <= '0';
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := count_blocks + 1;
|
count_blocks := count_blocks + 1;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
exit when blocks = 14;
|
exit when blocks = 14;
|
end loop;
|
end loop;
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 9;
|
exit when words = 9;
|
| Line 977... |
Line 1022... |
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_bytes <= b"01";
|
dut_bytes <= b"01";
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
| Line 1006... |
Line 1052... |
dut_ce <= '0';
|
dut_ce <= '0';
|
dut_di <= (others => '0');
|
dut_di <= (others => '0');
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_end <= '0';
|
dut_end <= '0';
|
dut_di_ack <= '0';
|
dut_di_wr <= '0';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_ce <= '1';
|
dut_ce <= '1';
|
dut_start <= '1';
|
dut_start <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_start <= '0';
|
dut_start <= '0';
|
dut_di_ack <= '1';
|
|
dut_bytes <= b"00";
|
dut_bytes <= b"00";
|
dut_di <= x"00000000";
|
dut_di <= x"00000000";
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := 0;
|
count_blocks := 0;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
loop
|
loop
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 15;
|
exit when words = 15;
|
end loop;
|
end loop;
|
|
dut_di_wr <= '0';
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
count_blocks := count_blocks + 1;
|
count_blocks := count_blocks + 1;
|
blocks <= count_blocks;
|
blocks <= count_blocks;
|
exit when blocks = 15623;
|
exit when blocks = 15623;
|
end loop;
|
end loop;
|
count_words := 0;
|
count_words := 0;
|
words <= count_words;
|
words <= count_words;
|
wait until dut_di_req = '1';
|
wait until dut_di_req = '1';
|
|
wait until pclk'event and pclk = '1';
|
|
dut_di_wr <= '1';
|
loop
|
loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
count_words := count_words + 1;
|
count_words := count_words + 1;
|
words <= count_words;
|
words <= count_words;
|
exit when words = 14;
|
exit when words = 14;
|
end loop;
|
end loop;
|
dut_end <= '1';
|
dut_end <= '1';
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
dut_end <= '0';
|
dut_end <= '0';
|
|
dut_di_wr <= '0';
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
if dut_error /= '1' and dut_do_valid /= '1' then
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
wait until pclk'event and pclk = '1';
|
wait until pclk'event and pclk = '1';
|
end loop;
|
end loop;
|
end if;
|
end if;
|
