| Line 37... |
Line 37... |
);
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);
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end scio;
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end scio;
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architecture rtl of scio is
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architecture rtl of scio is
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constant SLAVE_CNT : integer := 2;
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constant SLAVE_CNT : integer := 4;
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-- SLAVE_CNT <= 2**DECODE_BITS
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constant DECODE_BITS : integer := 2;
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-- number of bits that can be used inside the slave
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constant SLAVE_ADDR_BITS : integer := 4;
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constant SLAVE_ADDR_BITS : integer := 4;
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type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;
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type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;
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signal sc_rd, sc_wr : slave_bit;
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signal sc_rd, sc_wr : slave_bit;
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| Line 49... |
Line 52... |
signal sc_dout : slave_dout;
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signal sc_dout : slave_dout;
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type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);
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type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);
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signal sc_rdy_cnt : slave_rdy_cnt;
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signal sc_rdy_cnt : slave_rdy_cnt;
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signal rd_mux : std_logic;
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signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1;
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begin
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begin
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assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";
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sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
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-- What happens when sel_reg > SLAVE_CNT-1??
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rd_data <= sc_dout(sel_reg);
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rdy_cnt <= sc_rdy_cnt(sel_reg);
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--
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--
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-- Connect two simple test slaves
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-- Connect SLAVE_CNT simple test slaves
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--
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--
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gsl: for i in 0 to SLAVE_CNT-1 generate
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gsl: for i in 0 to SLAVE_CNT-1 generate
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wbsl: entity work.sc_test_slave
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sc_rd(i) <= rd when i=sel else '0';
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sc_wr(i) <= wr when i=sel else '0';
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scsl: entity work.sc_test_slave
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generic map (
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generic map (
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-- shall we use less address bits inside the slaves?
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-- shall we use less address bits inside the slaves?
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addr_bits => SLAVE_ADDR_BITS
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addr_bits => SLAVE_ADDR_BITS
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)
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)
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port map (
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port map (
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| Line 75... |
Line 90... |
rd_data => sc_dout(i),
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rd_data => sc_dout(i),
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rdy_cnt => sc_rdy_cnt(i)
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rdy_cnt => sc_rdy_cnt(i)
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);
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);
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end generate;
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end generate;
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--
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--
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-- Address decoding
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-- Register read mux selector
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--
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process(address, rd, wr)
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begin
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|
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-- How can we formulate this more elegant?
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sc_rd(0) <= '0';
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sc_wr(0) <= '0';
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sc_rd(1) <= '0';
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sc_wr(1) <= '0';
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|
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if address(SLAVE_ADDR_BITS)='0' then
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sc_rd(0) <= rd;
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sc_wr(0) <= wr;
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else
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sc_rd(1) <= rd;
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sc_wr(1) <= wr;
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end if;
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|
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end process;
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--
|
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-- Read mux selector
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--
|
--
|
process(clk, reset)
|
process(clk, reset)
|
begin
|
begin
|
|
|
if (reset='1') then
|
if (reset='1') then
|
rd_mux <= '0';
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sel_reg <= 0;
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elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
if rd='1' then
|
if rd='1' then
|
rd_mux <= address(SLAVE_ADDR_BITS);
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sel_reg <= sel;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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--
|
|
-- Read data and rdy_cnt mux
|
|
--
|
|
-- Or should we simple or the rdy_cnt values?
|
|
--
|
|
process(rd_mux, sc_dout, sc_rdy_cnt)
|
|
begin
|
|
|
|
if rd_mux='0' then
|
|
rd_data <= sc_dout(0);
|
|
rdy_cnt <= sc_rdy_cnt(0);
|
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else
|
|
rd_data <= sc_dout(1);
|
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rdy_cnt <= sc_rdy_cnt(1);
|
|
end if;
|
|
end process;
|
|
|
|
end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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