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-- $Id: input_fm.vhdl,v 1.1.1.1 2005-01-04 02:05:56 arif_endro Exp $
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-- $Id: input_fm.vhdl,v 1.2 2005-01-07 08:45:59 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Input signal FM
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-- Title : Input signal FM
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : input_fm.vhdl
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-- File : input_fm.vhdl
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process (clock, clear)
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process (clock, clear)
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begin
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begin
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-- if (clear = '1') then
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-- if (clear = '1') then
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-- counter (09 downto 0) <= (others => B"0000000000");
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-- counter (09 downto 0) <= (others => B"0000000000");
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-- elsif (((clock = '1') and clock'event) and (not(clear = '1')) then
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-- elsif (((clock = '1') and clock'event) and (not(clear = '1')) then
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if (((clock = '1') and (not( clear = '1'))) and clock'event) then
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if (clear = '1') then
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counter <= (others => '0');
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test_signal_fm <= (others => '0');
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test_signal_fmTri <= (others => '0');
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elsif (((clock = '1') and (not( clear = '1'))) and clock'event) then
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counter(09 downto 0) <= counter_tmp(09 downto 0);
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counter(09 downto 0) <= counter_tmp(09 downto 0);
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-- clock_out <= clock;
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-- clock_out <= clock;
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test_signal_fm <= test_signal_fm_int;
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test_signal_fm <= test_signal_fm_int;
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test_signal_fmTri <= test_signal_fmTri_int;
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test_signal_fmTri <= test_signal_fmTri_int;
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elsif (clear = '1') then
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counter <= (others => '0');
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test_signal_fm <= (others => '0');
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test_signal_fmTri <= (others => '0');
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end if;
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end if;
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end process;
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end process;
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with counter (09 downto 0) select
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with counter (09 downto 0) select
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test_signal_fm_int <=
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test_signal_fm_int <=
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