| Line 1... |
Line 1... |
-- $Id: input_fm.vhdl,v 1.1.1.1 2005-01-04 02:05:56 arif_endro Exp $
|
-- $Id: input_fm.vhdl,v 1.2 2005-01-07 08:45:59 arif_endro Exp $
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : Input signal FM
|
-- Title : Input signal FM
|
-- Project : FM Receiver
|
-- Project : FM Receiver
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : input_fm.vhdl
|
-- File : input_fm.vhdl
|
| Line 91... |
Line 91... |
process (clock, clear)
|
process (clock, clear)
|
begin
|
begin
|
-- if (clear = '1') then
|
-- if (clear = '1') then
|
-- counter (09 downto 0) <= (others => B"0000000000");
|
-- counter (09 downto 0) <= (others => B"0000000000");
|
-- elsif (((clock = '1') and clock'event) and (not(clear = '1')) then
|
-- elsif (((clock = '1') and clock'event) and (not(clear = '1')) then
|
if (((clock = '1') and (not( clear = '1'))) and clock'event) then
|
if (clear = '1') then
|
|
counter <= (others => '0');
|
|
test_signal_fm <= (others => '0');
|
|
test_signal_fmTri <= (others => '0');
|
|
elsif (((clock = '1') and (not( clear = '1'))) and clock'event) then
|
counter(09 downto 0) <= counter_tmp(09 downto 0);
|
counter(09 downto 0) <= counter_tmp(09 downto 0);
|
-- clock_out <= clock;
|
-- clock_out <= clock;
|
test_signal_fm <= test_signal_fm_int;
|
test_signal_fm <= test_signal_fm_int;
|
test_signal_fmTri <= test_signal_fmTri_int;
|
test_signal_fmTri <= test_signal_fmTri_int;
|
elsif (clear = '1') then
|
|
counter <= (others => '0');
|
|
test_signal_fm <= (others => '0');
|
|
test_signal_fmTri <= (others => '0');
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
with counter (09 downto 0) select
|
with counter (09 downto 0) select
|
test_signal_fm_int <=
|
test_signal_fm_int <=
|
