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-- $Id: bench.vhdl,v 1.1.1.1 2005-01-04 02:05:56 arif_endro Exp $
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-- $Id: bench.vhdl,v 1.2 2005-01-10 02:33:54 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Test Bench
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-- Title : Test Bench
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : bench.vhdl
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-- File : bench.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2004/12/23
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-- Created : 2004/12/23
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-- Last update :
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-- Last update : 2005/01/08
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-- Simulators : Modelsim 6.0
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-- Simulators : Modelsim 6.0
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Test bench for FM receiver
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-- Description : Test bench for FM receiver
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use IEEE.STD_LOGIC_unsigned.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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entity bench is
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entity bench is
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port (
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port (
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clock : in bit;
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clock : in bit;
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reset : in bit
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reset : in bit;
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-- test_signal_fm : out bit_vector (07 downto 0);
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output_fm : out bit_vector (11 downto 0);
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-- test_signal_fmTri : out bit_vector (07 downto 0);
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output_fmTri : out bit_vector (11 downto 0)
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-- output_fm : out bit_vector (11 downto 0)
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);
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);
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-- port (
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-- clock : out bit;
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-- fmout : out bit;
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-- reset : out bit;
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-- );
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end bench;
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end bench;
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architecture structural of bench is
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architecture structural of bench is
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component fm
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component fm
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port (
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port (
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test_signal_fm : out bit_vector (07 downto 0);
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test_signal_fm : out bit_vector (07 downto 0);
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test_signal_fmTri: out bit_vector (07 downto 0)
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test_signal_fmTri: out bit_vector (07 downto 0)
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);
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);
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end component;
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end component;
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-- signal clock : bit;
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-- signal reset : bit;
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signal test_signal_fm : bit_vector (07 downto 0);
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signal test_signal_fm : bit_vector (07 downto 0);
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signal test_signal_fmTri : bit_vector (07 downto 0);
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signal test_signal_fmTri : bit_vector (07 downto 0);
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signal output_fm : bit_vector (11 downto 0);
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begin
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begin
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-- reset <= '0';
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-- process
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-- variable run_time : time := 1024ns;
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-- begin
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-- wait for run_time;
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-- clear <= '1';
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-- reset <= '1';
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-- exit;
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-- end process;
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myinput : input_fm
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myinput : input_fm
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port map (
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port map (
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clock => clock,
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clock => clock,
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clear => reset,
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clear => reset,
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test_signal_fm => test_signal_fm,
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test_signal_fm => test_signal_fm,
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test_signal_fmTri=> test_signal_fmTri
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test_signal_fmTri=> test_signal_fmTri
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);
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);
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myfm : fm
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myfm : fm
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port map (
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port map (
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CLK => clock,
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CLK => clock,
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RESET => reset,
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RESET => reset,
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FMIN => test_signal_fm,
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FMIN => test_signal_fm,
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DMOUT (11 downto 0) => output_fm
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DMOUT (11 downto 0) => output_fm
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);
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);
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myfmTri : fm
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port map (
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CLK => clock,
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RESET => reset,
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FMIN => test_signal_fmTri,
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DMOUT (11 downto 0) => output_fmTri
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);
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end structural;
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end structural;
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No newline at end of file
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No newline at end of file
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