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-- $Id: chipscope_modelsim_view.vhdl,v 1.1 2005-01-11 03:52:22 arif_endro Exp $
-- ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif Endro Nugroho
-- Title      :  Viewer Chipscope output to modelsim
-- All rights reserved.
-- Project    :  FM Receiver
-- 
-------------------------------------------------------------------------------
-- Redistribution and use in source and binary forms, with or without
-- File        : chipscope_modelsim_view.vhdl
-- modification, are permitted provided that the following conditions
-- Author      : Arif E. Nugroho
-- are met:
-- Created     : 2005/01/10
-- 
-- Last update : 
-- 1. Redistributions of source code must retain the above copyright
-- Simulators  : Modelsim 6.0
--    notice, this list of conditions and the following disclaimer.
-- Synthesizers: 
-- 2. Redistributions in binary form must reproduce the above copyright
-- Target      : 
--    notice, this list of conditions and the following disclaimer in the
-------------------------------------------------------------------------------
--    documentation and/or other materials provided with the distribution.
-- Description : To analyze exported ASCII output of ChipScope Analyser to 
-- 
--               Modelsim
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-------------------------------------------------------------------------------
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- Copyright (c) 2005 Arif E. Nugroho
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- This VHDL design file is an open design; you can redistribute it and/or
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- modify it and/or implement it after contacting the author
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-------------------------------------------------------------------------------
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 
-- POSSIBILITY OF SUCH DAMAGE.
 
-- 
 
-- End Of License.
 
-- ------------------------------------------------------------------------
 
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

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