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-- $Id: adder_12bit.vhdl,v 1.3 2005-03-04 08:06:13 arif_endro Exp $
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-- $Id: adder_12bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 12 bit
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-- Title : Adder 12 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_12bit.vhdl
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-- File : adder_12bit.vhdl
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);
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);
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end component;
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end component;
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-- internal signal
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-- internal signal
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signal over12 : bit;
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signal over12 : bit;
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signal adder12_output_int : bit_vector (12 downto 0);
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signal adder12_output_int : bit_vector (11 downto 0);
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signal c00 : bit;
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signal c00 : bit;
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signal c01 : bit;
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signal c01 : bit;
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signal c02 : bit;
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signal c02 : bit;
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signal c03 : bit;
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signal c03 : bit;
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signal c04 : bit;
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signal c04 : bit;
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Line 76... |
signal c08 : bit;
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signal c08 : bit;
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signal c09 : bit;
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signal c09 : bit;
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signal c10 : bit;
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signal c10 : bit;
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signal c11 : bit;
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signal c11 : bit;
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signal c12 : bit;
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signal c12 : bit;
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signal ov : bit;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over12 <= (addend_12bit (11) xor augend_12bit (11));
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over12 <= (addend_12bit (11) xor augend_12bit (11));
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adder12_output_int (12) <= ((adder12_output_int (11) and over12) or
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ov <= ((adder12_output_int (11) and over12) or
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(c12 and (not (over12))));
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(c12 and (not (over12))));
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adder12_output <= adder12_output_int;
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adder12_output(11 downto 00) <= adder12_output_int;
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adder12_output(12) <= ov;
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fa11 : fulladder
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fa11 : fulladder
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port map (
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port map (
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addend => addend_12bit(11),
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addend => addend_12bit(11),
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augend => augend_12bit(11),
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augend => augend_12bit(11),
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