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-- $Id: adder_13bit.vhdl,v 1.3 2005-03-04 08:06:14 arif_endro Exp $
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-- $Id: adder_13bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 13 bit
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-- Title : Adder 13 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_13bit.vhdl
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-- File : adder_13bit.vhdl
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Line 76... |
signal c10 : bit;
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signal c10 : bit;
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signal c11 : bit;
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signal c11 : bit;
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signal c12 : bit;
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signal c12 : bit;
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signal c13 : bit;
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signal c13 : bit;
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signal over13 : bit;
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signal over13 : bit;
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signal adder13_output_int : bit_vector (13 downto 0);
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signal adder13_output_int : bit_vector (12 downto 0);
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signal ov : bit;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over13 <= (addend_13bit (12) xor augend_13bit (12));
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over13 <= (addend_13bit (12) xor augend_13bit (12));
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adder13_output_int(13) <= ((adder13_output_int(12) and over13) or
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ov <= ((adder13_output_int(12) and over13) or
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(c13 and (not (over13))));
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(c13 and (not (over13))));
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adder13_output <= adder13_output_int;
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adder13_output(12 downto 00) <= adder13_output_int;
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adder13_output(13) <= ov;
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fa12 : fulladder
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fa12 : fulladder
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port map (
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port map (
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addend => addend_13bit(12),
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addend => addend_13bit(12),
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augend => augend_13bit(12),
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augend => augend_13bit(12),
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