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Rev 22 |
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-- $Id: adder_14bit.vhdl,v 1.3 2005-03-04 08:06:15 arif_endro Exp $
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-- $Id: adder_14bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 14 bit
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-- Title : Adder 14 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_14bit.vhdl
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-- File : adder_14bit.vhdl
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Line 77... |
signal c11 : bit;
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signal c11 : bit;
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signal c12 : bit;
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signal c12 : bit;
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signal c13 : bit;
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signal c13 : bit;
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signal c14 : bit;
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signal c14 : bit;
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signal over14 : bit;
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signal over14 : bit;
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signal adder14_output_int : bit_vector (14 downto 0);
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signal adder14_output_int : bit_vector (13 downto 0);
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signal ov : bit;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over14 <= (addend_14bit (13) xor augend_14bit (13));
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over14 <= (addend_14bit (13) xor augend_14bit (13));
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adder14_output_int (14) <= ((adder14_output_int (13) and over14) or
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ov <= ((adder14_output_int (13) and over14) or
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(c14 and (not (over14))));
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(c14 and (not (over14))));
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adder14_output <= adder14_output_int;
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adder14_output(13 downto 00) <= adder14_output_int;
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adder14_output(14) <= ov;
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fa13 : fulladder
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fa13 : fulladder
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port map (
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port map (
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addend => addend_14bit(13),
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addend => addend_14bit(13),
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augend => augend_14bit(13),
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augend => augend_14bit(13),
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