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-- $Id: adder_15bit.vhdl,v 1.2 2005-02-21 06:54:36 arif_endro Exp $
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-- $Id: adder_15bit.vhdl,v 1.3 2005-03-04 08:06:16 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 15 bit
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-- Title : Adder 15 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_15bit.vhdl
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-- File : adder_15bit.vhdl
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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entity adder_15bit is
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entity adder_15bit is
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port (
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port (
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addend_15bit : in bit_vector (14 downto 0);
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addend_15bit : in bit_vector (14 downto 0);
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augend_15bit : in bit_vector (14 downto 0);
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augend_15bit : in bit_vector (14 downto 0);
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