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-- $Id: adder_15bit.vhdl,v 1.3 2005-03-04 08:06:16 arif_endro Exp $
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-- $Id: adder_15bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 15 bit
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-- Title : Adder 15 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_15bit.vhdl
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-- File : adder_15bit.vhdl
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Line 78... |
signal c12 : bit;
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signal c12 : bit;
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signal c13 : bit;
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signal c13 : bit;
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signal c14 : bit;
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signal c14 : bit;
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signal c15 : bit;
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signal c15 : bit;
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signal over15 : bit;
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signal over15 : bit;
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signal adder15_output_int : bit_vector (15 downto 0);
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signal adder15_output_int : bit_vector (14 downto 0);
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signal ov : bit;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over15 <= (addend_15bit (14) xor augend_15bit (14));
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over15 <= (addend_15bit (14) xor augend_15bit (14));
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adder15_output_int (15) <= ((adder15_output_int (14) and over15) or
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ov <= ((adder15_output_int (14) and over15) or
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(c15 and (not (over15))));
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(c15 and (not (over15))));
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adder15_output <= adder15_output_int;
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adder15_output(14 downto 00) <= adder15_output_int;
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adder15_output(15) <= ov;
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fa14 : fulladder
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fa14 : fulladder
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port map (
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port map (
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addend => addend_15bit(14),
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addend => addend_15bit(14),
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augend => augend_15bit(14),
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augend => augend_15bit(14),
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