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-- $Id: adder_16bit.vhdl,v 1.3 2005-03-04 08:06:16 arif_endro Exp $
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-- $Id: adder_16bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 16 bit
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-- Title : Adder 16 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_16bit.vhdl
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-- File : adder_16bit.vhdl
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Line 79... |
signal c13 : bit;
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signal c13 : bit;
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signal c14 : bit;
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signal c14 : bit;
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signal c15 : bit;
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signal c15 : bit;
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signal c16 : bit;
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signal c16 : bit;
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signal over16 : bit;
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signal over16 : bit;
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signal adder16_output_int : bit_vector (16 downto 0);
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signal adder16_output_int : bit_vector (15 downto 0);
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signal ov : bit;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over16 <= (addend_16bit (15) xor augend_16bit (15));
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over16 <= (addend_16bit (15) xor augend_16bit (15));
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adder16_output_int (16) <= ((adder16_output_int (15) and over16) or
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ov <= ((adder16_output_int (15) and over16) or
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(c16 and (not (over16))));
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(c16 and (not (over16))));
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adder16_output <= adder16_output_int;
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adder16_output(15 downto 00) <= adder16_output_int;
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adder16_output(16) <= ov;
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fa15 : fulladder
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fa15 : fulladder
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port map (
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port map (
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addend => addend_16bit(15),
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addend => addend_16bit(15),
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augend => augend_16bit(15),
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augend => augend_16bit(15),
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