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-- $Id: fir.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
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-- $Id: fir.vhdl,v 1.2 2005-02-21 06:36:55 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : FIR Low pass filter
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-- Title : FIR Low pass filter
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : fir.vhdl
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-- File : fir.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2004/10/30
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-- Created : 2004/10/30
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-- Last update : 2004/12/31
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-- Last update :
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-- Simulators : Modelsim 6.0
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-- Simulators :
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : FIR low pass filter
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-- Description : FIR low pass filter
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2004 Arif E. Nugroho
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-- Copyright (C) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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--
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-------------------------------------------------------------------------------
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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addend_15bit(14 downto 0) => result_adder13,
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addend_15bit(14 downto 0) => result_adder13,
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augend_15bit(14 downto 0) => result_adder14,
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augend_15bit(14 downto 0) => result_adder14,
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adder15_output => result_adder15
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adder15_output => result_adder15
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);
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);
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fir_out(11) <= (result_adder15(15) and not(clear)); -- 1
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fir_out(11) <= (result_adder15(15)); -- 1
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fir_out(10) <= (result_adder15(15) and not(clear)); -- 1/2
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fir_out(10) <= (result_adder15(15)); -- 1/2
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fir_out(09) <= (result_adder15(15) and not(clear)); -- 1/4
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fir_out(09) <= (result_adder15(15)); -- 1/4
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fir_out(08) <= (result_adder15(15) and not(clear)); -- 1/8
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fir_out(08) <= (result_adder15(15)); -- 1/8
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fir_out(07) <= (result_adder15(15) and not(clear)); -- 1/16
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fir_out(07) <= (result_adder15(15)); -- 1/16
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fir_out(06) <= (result_adder15(14) and not(clear));
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fir_out(06) <= (result_adder15(14));
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fir_out(05) <= (result_adder15(13) and not(clear));
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fir_out(05) <= (result_adder15(13));
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fir_out(04) <= (result_adder15(12) and not(clear));
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fir_out(04) <= (result_adder15(12));
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fir_out(03) <= (result_adder15(11) and not(clear));
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fir_out(03) <= (result_adder15(11));
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fir_out(02) <= (result_adder15(10) and not(clear));
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fir_out(02) <= (result_adder15(10));
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fir_out(01) <= (result_adder15(09) and not(clear));
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fir_out(01) <= (result_adder15(09));
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fir_out(00) <= (result_adder15(08) and not(clear));
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fir_out(00) <= (result_adder15(08));
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process (clock, clear)
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process (clock)
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begin
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begin
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-- if (((clock = '1') and (not(clear) = '1')) and clock'event) then
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if ((clock = '1') and clock'event) then
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if (clear = '1') then
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dmout <= (others => '0');
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elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
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fir_in_02 <= fir_in_01;
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fir_in_02 <= fir_in_01;
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fir_in_03 <= fir_in_02;
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fir_in_03 <= fir_in_02;
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fir_in_04 <= fir_in_03;
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fir_in_04 <= fir_in_03;
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fir_in_05 <= fir_in_04;
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fir_in_05 <= fir_in_04;
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fir_in_15 <= fir_in_14;
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fir_in_15 <= fir_in_14;
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fir_in_16 <= fir_in_15;
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fir_in_16 <= fir_in_15;
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dmout <= fir_out;
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dmout <= fir_out;
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-- elsif (clear = '1') then -- can't be synthesized in Xilinx
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-- dmout <= (others => '0');
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end if;
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end if;
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end process;
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end process;
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end structural;
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end structural;
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No newline at end of file
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No newline at end of file
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