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Rev 23 |
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-- $Id: fir.vhdl,v 1.4 2005-03-12 04:18:38 arif_endro Exp $
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-- $Id: fir.vhdl,v 1.5 2008-06-26 06:16:04 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : FIR Low pass filter
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-- Title : FIR Low pass filter
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : fir.vhdl
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-- File : fir.vhdl
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Line 243... |
fir_out(03) <= (result_adder15(07));
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fir_out(03) <= (result_adder15(07));
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fir_out(02) <= (result_adder15(06));
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fir_out(02) <= (result_adder15(06));
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fir_out(01) <= (result_adder15(05));
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fir_out(01) <= (result_adder15(05));
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fir_out(00) <= (result_adder15(04));
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fir_out(00) <= (result_adder15(04));
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process (clock, clear)
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-- 20080625
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-- fixme
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-- how to enable clear signal in here... :(
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-- process (clock, clear)
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process (clock)
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begin
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begin
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if (clear = '1') then
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-- if (clear = '1') then
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if ((clock = '1') and clock'event) then
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dmout <= (others => '0');
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-- dmout <= (others => '0');
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elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
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-- elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
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fir_in_02 <= fir_in_01;
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fir_in_02 <= fir_in_01;
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fir_in_03 <= fir_in_02;
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fir_in_03 <= fir_in_02;
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fir_in_04 <= fir_in_03;
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fir_in_04 <= fir_in_03;
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fir_in_05 <= fir_in_04;
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fir_in_05 <= fir_in_04;
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