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[/] [simple_fm_receiver/] [trunk/] [source/] [fm.vhdl] - Diff between revs 2 and 13

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-- $Id: fm.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
-- $Id: fm.vhdl,v 1.2 2005-02-21 06:54:44 arif_endro Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title       : FM core component
-- Title       : FM core component
-- Project     : FM Receiver 
-- Project     : FM Receiver 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File        : fm.vhdl
-- File        : fm.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2004/12/06
-- Created     : 2004/12/06
-- Last update : 2005/01/03 
-- Last update : 2005/01/03 
-- Simulators  : Modelsim 6.0
-- Simulators  : 
-- Synthesizers: 
-- Synthesizers: 
-- Target      : 
-- Target      : 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Description : FM core component to connect all other component
-- Description : FM core component to connect all other component
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2004 Arif E. Nugroho
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- 
 
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
 
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
 
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
 
-- ASSOCIATED DISCLAIMER.
 
-- 
 
-------------------------------------------------------------------------------
 
-- 
 
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
 
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- 
 
-------------------------------------------------------------------------------
 
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_arith.ALL;
 
 

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