| Line 1... |
Line 1... |
-- $Id: fulladder.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
|
-- $Id: fulladder.vhdl,v 1.2 2005-02-21 06:54:49 arif_endro Exp $
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : Full Adder component
|
-- Title : Full Adder component
|
-- Project : FM Receiver
|
-- Project : FM Receiver
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : fulladder.vhdl
|
-- File : fulladder.vhdl
|
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
|
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
|
-- Created : 2004/12/01
|
-- Created : 2004/12/01
|
-- Last update :
|
-- Last update :
|
-- Simulators : Modelsim 6.0
|
-- Simulators :
|
-- Synthesizers:
|
-- Synthesizers:
|
-- Target :
|
-- Target :
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description : Simple one bit adder with carry
|
-- Description : Simple one bit adder with carry
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Copyright (c) 2004 Arif E. Nugroho
|
-- Copyright (C) 2004 Arif E. Nugroho
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- modify it and/or implement it after contacting the author
|
-- modify it and/or implement it after contacting the author
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
|
|
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
|
|
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
|
|
-- ASSOCIATED DISCLAIMER.
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
--
|
|
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
|
|
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_arith.ALL;
|
use IEEE.STD_LOGIC_arith.ALL;
|
|
|
