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# $Id: modelsim.do,v 1.2 2005-03-12 04:18:38 arif_endro Exp $
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# -----------------------------------------------------------------------------
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# Title : ModelSim do file
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# Project : FM Receiver
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# -----------------------------------------------------------------------------
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# File : ModelSim do file
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# Author : "Arif E. Nugroho"
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# Created :
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# Last update :
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# Simulators : Modelsim 6.0
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# Synthesizers:
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# Target :
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# -----------------------------------------------------------------------------
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# Description : modelsim do file
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# -----------------------------------------------------------------------------
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# Copyright (C) 2005 Arif E. Nugroho
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# -----------------------------------------------------------------------------
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# -----------------------------------------------------------------------------
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#
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# THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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# PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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# ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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# ASSOCIATED DISCLAIMER.
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#
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# -----------------------------------------------------------------------------
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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# EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# -----------------------------------------------------------------------------
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# Destroy output window
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destroy .wave;
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destroy .wave;
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destroy .list;
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destroy .list;
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# Create work library
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vlib work;
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vlib work;
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# Compile all source
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vcom *.vhdl;
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vcom *.vhdl;
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# Simulate the design
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vsim bench;
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vsim bench;
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# Show the output signal to wave window
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add wave /bench/clock;
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add wave /bench/clock;
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add wave /bench/reset;
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add wave /bench/reset;
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/fmin
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/fmin
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/output_nco
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/output_nco
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add wave -height 80 -scale 1. -format Analog-Step /bench/myfm/phase_output
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add wave -height 80 -scale 1. -format Analog-Step /bench/myfm/phase_output
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add wave -height 80 -scale .0002 -format Analog-Step /bench/myfm/mynco/myaddacc/result
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add wave -height 80 -scale .0002 -format Analog-Step /bench/myfm/mynco/myaddacc/result
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/loop_out
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add wave -height 80 -scale .1 -format Analog-Step /bench/myfm/loop_out
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add wave -height 80 -scale 1. -format Analog-Step /bench/myfm/dmout
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add wave -height 80 -scale 1. -format Analog-Step /bench/myfm/dmout
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# force -freeze sim:/bench/clock 1 0, 0 {50 ns} -r 100
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# force -freeze sim:/bench/reset 0 0
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# run -all
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# run 102400ns
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