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-- $Id: rom.vhdl,v 1.2 2005-02-21 06:54:54 arif_endro Exp $
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-- $Id: rom.vhdl,v 1.3 2005-03-04 08:06:21 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : ROM
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-- Title : ROM
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : rom.vhdl
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-- File : rom.vhdl
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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entity rom is
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entity rom is
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port (
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port (
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address : in bit_vector (9 downto 0);
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address : in bit_vector (9 downto 0);
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data : out bit_vector (7 downto 0)
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data : out bit_vector (7 downto 0)
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