| Line 15... |
Line 15... |
decoder/Project/Lattice_FPGA_Build/promote.xml
|
decoder/Project/Lattice_FPGA_Build/promote.xml
|
Target Vendor: LATTICE
|
Target Vendor: LATTICE
|
Target Device: LFE5UM5G-45FCABGA381
|
Target Device: LFE5UM5G-45FCABGA381
|
Target Performance: 8
|
Target Performance: 8
|
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
|
Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
|
Mapped on: 01/13/17 00:54:48
|
Mapped on: 01/17/17 01:36:37
|
|
|
Design Summary
|
Design Summary
|
--------------
|
--------------
|
|
|
Number of registers: 0 out of 44457 (0%)
|
Number of registers: 13 out of 44457 (0%)
|
PFU registers: 0 out of 43848 (0%)
|
PFU registers: 12 out of 43848 (0%)
|
PIO registers: 0 out of 609 (0%)
|
PIO registers: 1 out of 609 (0%)
|
Number of SLICEs: 0 out of 21924 (0%)
|
Number of SLICEs: 65 out of 21924 (0%)
|
SLICEs as Logic/ROM: 0 out of 21924 (0%)
|
SLICEs as Logic/ROM: 65 out of 21924 (0%)
|
SLICEs as RAM: 0 out of 16443 (0%)
|
SLICEs as RAM: 0 out of 16443 (0%)
|
SLICEs as Carry: 0 out of 21924 (0%)
|
SLICEs as Carry: 5 out of 21924 (0%)
|
Number of LUT4s: 0 out of 43848 (0%)
|
Number of LUT4s: 127 out of 43848 (0%)
|
Number used as logic LUTs: 0
|
Number used as logic LUTs: 117
|
Number used as distributed RAM: 0
|
Number used as distributed RAM: 0
|
Number used as ripple logic: 0
|
Number used as ripple logic: 10
|
Number used as shift registers: 0
|
Number used as shift registers: 0
|
Number of PIO sites used: 16 out of 203 (8%)
|
Number of PIO sites used: 20 out of 203 (10%)
|
|
Number of PIO sites used for single ended IOs: 18
|
|
Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
|
|
comps in NCD)
|
Number of block RAMs: 0 out of 108 (0%)
|
Number of block RAMs: 0 out of 108 (0%)
|
Number of GSRs: 0 out of 1 (0%)
|
Number of GSRs: 1 out of 1 (100%)
|
JTAG used : No
|
JTAG used : No
|
Readback used : No
|
Readback used : No
|
Oscillator used : No
|
Oscillator used : No
|
Startup used : No
|
Startup used : No
|
DTR used : No
|
DTR used : No
|
| Line 55... |
Line 58... |
Number of DCU Channels: 0 out of 4 (0%)
|
Number of DCU Channels: 0 out of 4 (0%)
|
Number of EXTREFs: 0 out of 2 (0%)
|
Number of EXTREFs: 0 out of 2 (0%)
|
Notes:-
|
Notes:-
|
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
distributed RAMs) + 2*(Number of ripple logic)
|
distributed RAMs) + 2*(Number of ripple logic)
|
2. Number of logic LUT4s does not include count of distributed RAM and
|
|
ripple logic.
|
|
|
|
|
|
Page 1
|
Page 1
|
|
|
|
|
|
|
|
|
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
|
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
|
|
|
Design Summary (cont)
|
Design Summary (cont)
|
---------------------
|
---------------------
|
|
2. Number of logic LUT4s does not include count of distributed RAM and
|
|
ripple logic.
|
|
|
Number Of Mapped DSP Components:
|
Number Of Mapped DSP Components:
|
--------------------------------
|
--------------------------------
|
MULT18X18D 0
|
MULT18X18D 0
|
MULT9X9D 0
|
MULT9X9D 0
|
ALU54B 0
|
ALU54B 0
|
| Line 80... |
Line 83... |
PRADD9A 0
|
PRADD9A 0
|
--------------------------------
|
--------------------------------
|
Number of Used DSP MULT Sites: 0 out of 144 (0 %)
|
Number of Used DSP MULT Sites: 0 out of 144 (0 %)
|
Number of Used DSP ALU Sites: 0 out of 72 (0 %)
|
Number of Used DSP ALU Sites: 0 out of 72 (0 %)
|
Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
|
Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
|
Number of clocks: 0
|
Number of clocks: 1
|
Number of Clock Enables: 0
|
Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
|
Number of LSRs: 0
|
Number of Clock Enables: 1
|
|
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads, 5 LSLICEs
|
|
Number of local set/reset loads for net n_rst_c merged into GSR: 8
|
|
Number of LSRs: 1
|
|
Net n_rst_c: 3 loads, 2 LSLICEs
|
Number of nets driven by tri-state buffers: 0
|
Number of nets driven by tri-state buffers: 0
|
Top 10 highest fanout non-clock nets:
|
Top 10 highest fanout non-clock nets:
|
|
Net symbol_scan_cntr[1]: 107 loads
|
|
Net symbol_scan_cntr[2]: 107 loads
|
|
Net symbol_scan_cntr[3]: 107 loads
|
|
Net symbol_scan_cntr[5]: 86 loads
|
|
Net symbol_scan_cntr[6]: 57 loads
|
|
Net symbol_scan_cntr[4]: 29 loads
|
|
Net symbol_scan_cntr[0]: 15 loads
|
|
Net n_rst_c: 6 loads
|
|
Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
|
|
Net bttn_state_fifo[0]: 3 loads
|
|
|
|
|
|
|
|
|
Number of warnings: 1
|
Number of warnings: 4
|
Number of errors: 0
|
Number of errors: 0
|
|
|
|
|
Design Errors/Warnings
|
Design Errors/Warnings
|
----------------------
|
----------------------
|
|
|
WARNING - map: IO buffer missing for top level port button...logic will be
|
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
|
discarded.
|
ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
|
|
ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
|
|
preference has been disabled.
|
|
WARNING - map: Preference parsing results: 1 semantic error detected.
|
|
WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
|
|
WARNING - map: There are semantic errors in the preference file C:/Projects/sing
|
|
le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
|
|
iverwDecoder.lpf.
|
|
|
|
|
|
|
|
Page 2
|
|
|
|
|
|
|
|
|
|
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
|
|
|
IO (PIO) Attributes
|
IO (PIO) Attributes
|
-------------------
|
-------------------
|
|
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| IO Name | Direction | Levelmode | IO |
|
| IO Name | Direction | Levelmode | IO |
|
| | | IO_TYPE | Register |
|
| | | IO_TYPE | Register |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[0] | OUTPUT | LVCMOS25 | |
|
| disp_data[0] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
|
| clk | INPUT | LVDS | |
|
|
+---------------------+-----------+-----------+------------+
|
| disp_sel | OUTPUT | LVCMOS25 | |
|
| disp_sel | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[14] | OUTPUT | LVCMOS25 | |
|
| disp_data[14] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[13] | OUTPUT | LVCMOS25 | |
|
| disp_data[13] | OUTPUT | LVCMOS25 | |
|
| Line 124... |
Line 159... |
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[9] | OUTPUT | LVCMOS25 | |
|
| disp_data[9] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[8] | OUTPUT | LVCMOS25 | |
|
| disp_data[8] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
|
|
Page 2
|
|
|
|
|
|
|
|
|
|
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
|
|
|
|
IO (PIO) Attributes (cont)
|
|
--------------------------
|
|
| disp_data[7] | OUTPUT | LVCMOS25 | |
|
| disp_data[7] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[6] | OUTPUT | LVCMOS25 | |
|
| disp_data[6] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[5] | OUTPUT | LVCMOS25 | |
|
| disp_data[5] | OUTPUT | LVCMOS25 | |
|
| Line 148... |
Line 173... |
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[2] | OUTPUT | LVCMOS25 | |
|
| disp_data[2] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
| disp_data[1] | OUTPUT | LVCMOS25 | |
|
| disp_data[1] | OUTPUT | LVCMOS25 | |
|
+---------------------+-----------+-----------+------------+
|
+---------------------+-----------+-----------+------------+
|
|
| button | INPUT | LVCMOS25 | IN |
|
|
+---------------------+-----------+-----------+------------+
|
|
| n_rst | INPUT | LVCMOS25 | |
|
|
+---------------------+-----------+-----------+------------+
|
|
|
Removed logic
|
Removed logic
|
-------------
|
-------------
|
|
|
Block GSR_INST undriven or does not drive anything - clipped.
|
Signal n_rst_c_i was merged into signal n_rst_c
|
Block rst_pad undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/VCC undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
|
|
Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
|
|
Block clk_pad undriven or does not drive anything - clipped.
|
|
Signal GND undriven or does not drive anything - clipped.
|
Signal GND undriven or does not drive anything - clipped.
|
Signal VCC undriven or does not drive anything - clipped.
|
Signal VCC undriven or does not drive anything - clipped.
|
Signal rst undriven or does not drive anything - clipped.
|
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
|
Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
|
clipped.
|
Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
|
Signal N_1 undriven or does not drive anything - clipped.
|
Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
|
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
|
Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
|
|
Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
|
|
Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
|
|
Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
|
|
Signal rst_c undriven or does not drive anything - clipped.
|
|
Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
|
|
Signal clk_c undriven or does not drive anything - clipped.
|
|
Signal clk undriven or does not drive anything - clipped.
|
|
Block GND was optimized away.
|
|
Block VCC was optimized away.
|
|
|
|
Memory Usage
|
|
------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
|
|
|
Page 3
|
Page 3
|
|
|
|
|
|
|
|
|
Design: DisplayDriverWrapper Date: 01/13/17 00:54:48
|
Design: DisplayDriverWrapper Date: 01/17/17 01:36:37
|
|
|
Run Time and Memory Usage
|
|
-------------------------
|
|
|
|
Total CPU Time: 0 secs
|
|
Total REAL Time: 0 secs
|
|
Peak Memory Usage: 60 MB
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Removed logic (cont)
|
|
--------------------
|
|
clipped.
|
|
Block n_rst_pad_RNIQVTF was optimized away.
|
|
Block GND was optimized away.
|
|
Block VCC was optimized away.
|
|
|
|
Memory Usage
|
|
------------
|
|
|
|
|
|
|
|
|
|
GSR Usage
|
|
---------
|
|
|
|
GSR Component:
|
|
The local reset signal 'n_rst_c' of the design has been inferred as Global
|
|
Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
|
|
|
|
|
|
GSR Property:
|
|
The design components with GSR property set to ENABLED will respond to global
|
|
set reset while the components with GSR property set to DISABLED will
|
|
not.
|
|
|
|
|
|
Components on inferred reset domain with GSR Property disabled
|
|
--------------------------------------------------------------
|
|
|
|
These components have the GSR property set to DISABLED and are on the
|
|
inferred reset domain. The components will respond to the reset signal
|
|
'n_rst_c' via the local reset on the component and not the GSR component.
|
|
|
|
Type and number of components of the type:
|
|
Register = 4
|
|
|
|
Type and instance name of component:
|
|
Register : bttn_state_fifo[3]
|
|
Register : bttn_state_fifo_0io[0]
|
|
Register : bttn_state_fifo[1]
|
|
Register : bttn_state_fifo[2]
|
|
|
|
Run Time and Memory Usage
|
|
-------------------------
|
|
|
|
Total CPU Time: 1 secs
|
|
Total REAL Time: 2 secs
|
|
Peak Memory Usage: 152 MB
|
|
|
|
|
|
|
|
|
|
|
