| Line 2... |
Line 2... |
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
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Fri Jan 13 00:54:53 2017
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Tue Jan 17 01:36:43 2017
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C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
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C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
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DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
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DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
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DisplayDriverwDecoder_impl1.prf -gui -msgset
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DisplayDriverwDecoder_impl1.prf -gui -msgset
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
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| Line 15... |
Line 15... |
Preference file: DisplayDriverwDecoder_impl1.prf.
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Preference file: DisplayDriverwDecoder_impl1.prf.
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Level/ Number Worst Timing Worst Timing Run NCD
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 - - - - 06 Complete
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5_1 * 0 -1.238 7103 0.178 0 26 Complete
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* : Design saved.
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* : Design saved.
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Total (real) run time for 1-seed: 6 secs
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Total (real) run time for 1-seed: 26 secs
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par done!
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par done!
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Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
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Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
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Fri Jan 13 00:54:53 2017
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Tue Jan 17 01:36:43 2017
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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
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Preference file: DisplayDriverwDecoder_impl1.prf.
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Preference file: DisplayDriverwDecoder_impl1.prf.
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Placement level-cost: 5-1.
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Placement level-cost: 5-1.
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| Line 49... |
Line 49... |
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Ignore Preference Error(s): True
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Ignore Preference Error(s): True
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Device utilization summary:
|
Device utilization summary:
|
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PIO (prelim) 16/245 6% used
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PIO (prelim) 20/245 8% used
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16/203 7% bonded
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20/203 9% bonded
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IOLOGIC 1/245 <1% used
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SLICE 0/21924 0% used
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SLICE 65/21924 <1% used
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GSR 1/1 100% used
|
|
|
|
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Number of Signals: 0
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Number of Signals: 131
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Number of Connections: 0
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Number of Connections: 657
|
|
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Pin Constraint Summary:
|
Pin Constraint Summary:
|
16 out of 16 pins locked (100% locked).
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19 out of 19 pins locked (100% locked).
|
|
|
|
The following 1 signal is selected to use the primary clock routing resources:
|
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clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
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No signal is selected as Global Set/Reset.
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Starting Placer Phase 0.
|
|
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Finished Placer Phase 0. REAL time: 5 secs
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Signal n_rst_c is selected as Global Set/Reset.
|
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Starting Placer Phase 0.
|
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.........
|
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Finished Placer Phase 0. REAL time: 4 secs
|
|
|
Starting Placer Phase 1.
|
Starting Placer Phase 1.
|
|
.......................
|
Placer score = 0.
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Placer score = 63578.
|
Finished Placer Phase 1. REAL time: 5 secs
|
Finished Placer Phase 1. REAL time: 15 secs
|
|
|
Starting Placer Phase 2.
|
Starting Placer Phase 2.
|
.
|
.
|
Placer score = 0
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Placer score = 63553
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Finished Placer Phase 2. REAL time: 5 secs
|
Finished Placer Phase 2. REAL time: 15 secs
|
|
|
|
|
------------------ Clock Report ------------------
|
------------------ Clock Report ------------------
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|
|
Global Clock Resources:
|
Global Clock Resources:
|
CLK_PIN : 0 out of 12 (0%)
|
CLK_PIN : 0 out of 12 (0%)
|
GR_PCLK : 0 out of 12 (0%)
|
GR_PCLK : 1 out of 12 (8%)
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PLL : 0 out of 4 (0%)
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PLL : 0 out of 4 (0%)
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DCS : 0 out of 2 (0%)
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DCS : 0 out of 2 (0%)
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DCC : 0 out of 60 (0%)
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DCC : 0 out of 60 (0%)
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CLKDIV : 0 out of 4 (0%)
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CLKDIV : 0 out of 4 (0%)
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|
|
| Line 98... |
Line 103... |
Quadrant TR Clocks:
|
Quadrant TR Clocks:
|
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PRIMARY : 0 out of 16 (0%)
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PRIMARY : 0 out of 16 (0%)
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|
Quadrant BL Clocks:
|
Quadrant BL Clocks:
|
|
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1
|
|
|
PRIMARY : 0 out of 16 (0%)
|
PRIMARY : 1 out of 16 (6%)
|
|
|
Quadrant BR Clocks:
|
Quadrant BR Clocks:
|
|
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8
|
|
|
PRIMARY : 0 out of 16 (0%)
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PRIMARY : 1 out of 16 (6%)
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|
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Edge Clocks:
|
Edge Clocks:
|
|
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No edge clock selected.
|
No edge clock selected.
|
|
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| Line 115... |
Line 122... |
--------------- End of Clock Report ---------------
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--------------- End of Clock Report ---------------
|
|
|
|
|
+
|
+
|
I/O Usage Summary (final):
|
I/O Usage Summary (final):
|
16 out of 245 (6.5%) PIO sites used.
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20 out of 245 (8.2%) PIO sites used.
|
16 out of 203 (7.9%) bonded PIO sites used.
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20 out of 203 (9.9%) bonded PIO sites used.
|
Number of PIO comps: 16; differential: 0.
|
Number of PIO comps: 19; differential: 1.
|
Number of Vref pins used: 0.
|
Number of Vref pins used: 0.
|
|
|
I/O Bank Usage Summary:
|
I/O Bank Usage Summary:
|
+----------+----------------+------------+------------+------------+
|
+----------+----------------+------------+------------+------------+
|
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
+----------+----------------+------------+------------+------------+
|
+----------+----------------+------------+------------+------------+
|
| 0 | 0 / 27 ( 0%) | - | - | - |
|
| 0 | 0 / 27 ( 0%) | - | - | - |
|
| 1 | 0 / 33 ( 0%) | - | - | - |
|
| 1 | 0 / 33 ( 0%) | - | - | - |
|
| 2 | 0 / 32 ( 0%) | - | - | - |
|
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
|
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
|
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
|
| 6 | 1 / 33 ( 3%) | 2.5V | - | - |
|
| 6 | 3 / 33 ( 9%) | 2.5V | - | - |
|
| 7 | 0 / 32 ( 0%) | - | - | - |
|
| 7 | 0 / 32 ( 0%) | - | - | - |
|
| 8 | 1 / 13 ( 7%) | 2.5V | - | - |
|
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
|
+----------+----------------+------------+------------+------------+
|
+----------+----------------+------------+------------+------------+
|
|
|
Total placer CPU time: 3 secs
|
Total placer CPU time: 15 secs
|
|
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
|
|
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
|
0 connections routed; 657 unrouted.
|
Timing score: 0
|
Starting router resource preassignment
|
|
|
|
Completed router resource preassignment. Real time: 23 secs
|
|
|
|
Start NBR router at 01:37:06 01/17/17
|
|
|
|
*****************************************************************
|
|
Info: NBR allows conflicts(one node used by more than one signal)
|
|
in the earlier iterations. In each iteration, it tries to
|
|
solve the conflicts while keeping the critical connections
|
|
routed as short as possible. The routing process is said to
|
|
be completed when no conflicts exist and all connections
|
|
are routed.
|
|
Note: NBR uses a different method to calculate timing slacks. The
|
|
worst slack and total negative slack may not be the same as
|
|
that in TRCE report. You should always run TRCE to verify
|
|
your design.
|
|
*****************************************************************
|
|
|
|
Start NBR special constraint process at 01:37:06 01/17/17
|
|
|
|
Start NBR section for initial routing at 01:37:06 01/17/17
|
|
Level 1, iteration 1
|
|
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.227ns/-8.380ns; real time: 24 secs
|
|
Level 2, iteration 1
|
|
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
Level 3, iteration 1
|
|
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
Level 4, iteration 1
|
|
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
|
|
Info: Initial congestion level at 75% usage is 0
|
|
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
|
|
|
Start NBR section for normal routing at 01:37:07 01/17/17
|
|
Level 1, iteration 1
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
Level 2, iteration 1
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
Level 3, iteration 1
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
|
|
Start NBR section for performance tuning (iteration 1) at 01:37:07 01/17/17
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
|
|
Start NBR section for re-routing at 01:37:07 01/17/17
|
|
Level 4, iteration 1
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
|
|
|
Start NBR section for post-routing at 01:37:07 01/17/17
|
|
|
|
End NBR router with 0 unrouted connection
|
|
|
|
NBR Summary
|
|
-----------
|
|
Number of unrouted connections : 0 (0.00%)
|
|
Number of connections with timing violations : 9 (1.37%)
|
|
Estimated worst slack : -1.238ns
|
|
Timing score : 7103
|
|
-----------
|
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
|
|
|
|
|
|
|
Total CPU time 24 secs
|
|
Total REAL time: 25 secs
|
|
Completely routed.
|
|
End of route. 657 routed (100.00%); 0 unrouted.
|
|
|
|
Hold time timing score: 0, hold timing errors: 0
|
|
|
|
Timing score: 7103
|
|
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
|
|
|
|
All signals are completely routed.
|
All signals are completely routed.
|
|
|
|
|
PAR_SUMMARY::Run status = completed
|
PAR_SUMMARY::Run status = completed
|
PAR_SUMMARY::Number of unrouted conns = 0
|
PAR_SUMMARY::Number of unrouted conns = 0
|
PAR_SUMMARY::Worst slack> =
|
PAR_SUMMARY::Worst slack> = -1.238
|
PAR_SUMMARY::Timing score> =
|
PAR_SUMMARY::Timing score> = 7.103
|
PAR_SUMMARY::Worst slack> =
|
PAR_SUMMARY::Worst slack> = 0.178
|
PAR_SUMMARY::Timing score> =
|
PAR_SUMMARY::Timing score> = 0.000
|
PAR_SUMMARY::Number of errors = 0
|
PAR_SUMMARY::Number of errors = 0
|
|
|
Total CPU time to completion: 4 secs
|
Total CPU time to completion: 25 secs
|
Total REAL time to completion: 6 secs
|
Total REAL time to completion: 26 secs
|
|
|
par done!
|
par done!
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
