OpenCores
URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_scck.rpt] - Diff between revs 5 and 6

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 5 Rev 6
Line 1... Line 1...
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul  5 2016
# Synopsys Constraint Checker(syntax only), version maplat, Build 1498R, built Jul  5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
 
# Written on Fri Jan 13 00:54:39 2017
# Written on Tue Jan 17 01:19:11 2017
 
 
 
 
##### DESIGN INFO #######################################################
##### DESIGN INFO #######################################################
 
 
Top View:                "DisplayDriverWrapper"
Top View:                "DisplayDriverWrapper"
Line 21... Line 21...
Clock Summary
Clock Summary
*************
*************
 
 
Start                        Requested     Requested     Clock        Clock                     Clock
Start                        Requested     Requested     Clock        Clock                     Clock
Clock                        Frequency     Period        Type         Group                     Load
Clock                        Frequency     Period        Type         Group                     Load
-----------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
DisplayDriverWrapper|button     918.9 MHz     1.088         inferred     Autoconstr_clkgroup_0     8
=====================================================================================================
========================================================================================================
========================================================================================================
========================================================================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.