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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [impl1_cck.rpt] - Diff between revs 5 and 6

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# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul  5 2016
# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul  5 2016
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
 
 
# Written on Sun Jan 08 00:49:34 2017
# Written on Tue Jan 17 01:29:38 2017
 
 
 
 
##### DESIGN INFO #######################################################
##### DESIGN INFO #######################################################
 
 
Top View:                "DisplayDriverWrapper"
Top View:                "DisplayDriverWrapper"
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Clock Relationships
Clock Relationships
*******************
*******************
 
 
Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
-----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
===================================================================================================================================
DisplayDriverWrapper|clk                          DisplayDriverWrapper|clk                          |     1000.000         |     No paths         |     No paths         |     No paths
 
DisplayDriverWrapper|bttn_state_derived_clock     DisplayDriverWrapper|bttn_state_derived_clock     |     1000.000         |     No paths         |     No paths         |     No paths
 
===============================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
 
Unconstrained Start/End Points
Unconstrained Start/End Points
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p:disp_data[9]
p:disp_data[9]
p:disp_data[10]
p:disp_data[10]
p:disp_data[11]
p:disp_data[11]
p:disp_data[12]
p:disp_data[12]
p:disp_data[13]
p:disp_data[13]
 
p:disp_data[14]
p:disp_sel
p:disp_sel
p:rst
p:n_rst
 
 
 
 
Inapplicable constraints
Inapplicable constraints
************************
************************
 
 

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