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#-- Lattice Semiconductor Corporation Ltd.
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
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#-- Synplify OEM project file C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/launch_synplify.tcl
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#-- Written on Tue Jan 17 01:28:15 2017
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#-- Written on Tue Jan 17 23:37:07 2017
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project -close
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project -close
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set filename "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj"
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set filename "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1_syn.prj"
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if ([file exists "$filename"]) {
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if ([file exists "$filename"]) {
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project -load "$filename"
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project -load "$filename"
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Line 43... |
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}
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}
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#-- add_file options
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#-- add_file options
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add_file -vhdl "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
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add_file -vhdl "C:/lscc/diamond/3.8_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ASCIIDecoder.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/DistRomAsciiDecoder/DistRomAsciiDecoder/DistRomAsciiDecoder.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/ascii_decoder.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_w_decoder.vhd"
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add_file -vhdl -lib "work" "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/display_driver_wrapper.vhd"
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#-- top module name
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#-- top module name
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set_option -top_module {}
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set_option -top_module {}
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project -result_file {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi}
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project -result_file {C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1/impl1.edi}
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project -save "$filename"
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project -save "$filename"
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No newline at end of file
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No newline at end of file
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