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Line 1... |
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71001181
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1101672
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Warning
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Warning
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0
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE ASCII "G.L." ; ":
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Invalid Ascii char <.>.Invalid Ascii char <.>.
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
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21
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51001046
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1104062
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Warning
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Warning
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button
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1 semantic error
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51001030
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Warning
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n_rst_c
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51001230
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Warning
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
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35002000
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35002000
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| Line 115... |
Line 127... |
6
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6
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60001135
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2030012
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Info
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Warning
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1166052
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1166052
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Warning
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Warning
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logical
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logical
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button
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symbol_scan_cntr_cry_0_S0[0]
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button
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symbol_scan_cntr_cry_0_S0[0]
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1166052
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Warning
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logical
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symbol_scan_cntr_s_0_S1[7]
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symbol_scan_cntr_s_0_S1[7]
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1166052
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Warning
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logical
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symbol_scan_cntr_s_0_COUT[7]
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symbol_scan_cntr_s_0_COUT[7]
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1163101
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1163101
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Warning
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Warning
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1
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3
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2011000
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2011000
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| Line 153... |
Line 179... |
Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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2019991
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2019991
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Warning
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Warning
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MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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CD638
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C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd
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53
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11
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53
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19
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Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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2019991
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Warning
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CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
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CL169
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C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd
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54
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4
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54
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5
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Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
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2019991
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Warning
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CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
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CL169
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C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd
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54
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4
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54
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5
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Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
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2019991
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Warning
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MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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MT529
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MT529
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c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd
|
c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd
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76
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74
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8
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4
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76
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74
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9
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5
|
Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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2019993
|
2019993
|
Warning
|
Warning
|
MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
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MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
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MT420
|
MT420
|
Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
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Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
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No newline at end of file
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No newline at end of file
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