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##### START OF TIMING REPORT #####[
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##### START OF TIMING REPORT #####[
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# Timing Report written on Tue Jan 17 01:19:13 2017
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# Timing Report written on Wed Jan 18 01:08:17 2017
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#
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#
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Top view: DisplayDriverWrapper
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Top view: display_driver_wrapper
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Requested Frequency: 443.5 MHz
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Requested Frequency: 433.9 MHz
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Wire load mode: top
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Wire load mode: top
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Paths requested: 5
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Paths requested: 5
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Constraint File(s):
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Constraint File(s):
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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Performance Summary
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Performance Summary
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*******************
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*******************
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Worst slack in design: 0.884
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Worst slack in design: 0.439
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Requested Estimated Requested Estimated Clock Clock
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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Starting Clock Frequency Frequency Period Period Slack Type Group
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-------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
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display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
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=====================================================================================================================================
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====================================================================================================================================
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Clock Relationships
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Clock Relationships
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*******************
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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------------------------------------------------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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------------------------------------------------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|button DisplayDriverWrapper|button | 0.000 0.884 | No paths - | No paths - | No paths -
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display_driver_wrapper|clk display_driver_wrapper|clk | 0.000 0.439 | No paths - | No paths - | No paths -
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================================================================================================================================================
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==============================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Line 50... |
No IO constraint found
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No IO constraint found
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====================================
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====================================
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Detailed Report for Clock: DisplayDriverWrapper|button
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Detailed Report for Clock: display_driver_wrapper|clk
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====================================
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====================================
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Starting Points with Worst Slack
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Starting Points with Worst Slack
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********************************
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********************************
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Starting Arrival
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Instance Reference Type Pin Net Time Slack
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Clock
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Clock
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-------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------
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symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.559 0.884
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bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.587 0.439
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symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.527 0.884
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bttn_state_fifo[2] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[2] 0.587 0.439
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symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.653 0.979
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bttn_state_fifo_0io[0] display_driver_wrapper|clk IFS1P3JX Q bttn_state_fifo[0] 0.587 0.439
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symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.653 0.979
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symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[7] 0.559 0.884
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symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.653 0.979
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symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.653 0.979
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symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.653 0.979
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symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.653 0.979
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symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.653 0.979
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symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.653 0.979
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symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.653 0.979
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symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.653 0.979
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===============================================================================================================================
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symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.653 0.979
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symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.653 0.979
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========================================================================================================================
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Ending Points with Worst Slack
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Ending Points with Worst Slack
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******************************
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******************************
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Starting Required
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Instance Reference Type Pin Net Time Slack
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Clock
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Clock
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-----------------------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------------------------
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symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
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bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[0] 0.148 0.439
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symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 0.148 0.884
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bttn_state_fifo[2] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[1] 0.148 0.439
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symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 0.148 0.884
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bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX D bttn_state_fifo[2] 0.148 0.439
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symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 0.148 0.979
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bttn_state display_driver_wrapper|clk FD1S3AX D bttn_stateand 0.148 0.679
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symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 0.148 0.979
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symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 0.148 0.884
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symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 0.148 0.979
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symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
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symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 0.148 0.979
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symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
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symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 0.148 0.979
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symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
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symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 0.148 0.979
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symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
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=============================================================================================================================
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symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933
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=================================================================================================================================
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Worst Path Information
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Worst Path Information
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***********************
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***********************
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Path information for path number 1:
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Path information for path number 1:
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Propagation time: 1.032
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Propagation time: 0.587
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+ Clock delay at starting point: 0.000 (ideal)
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+ Clock delay at starting point: 0.000 (ideal)
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- Requested Period: 0.000
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- Requested Period: 0.000
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- Hold time: 0.148
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- Hold time: 0.148
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- Clock delay at ending point: 0.000 (ideal)
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- Clock delay at ending point: 0.000 (ideal)
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= Slack (critical) : 0.884
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= Slack (critical) : 0.439
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Number of logic level(s): 1
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Number of logic level(s): 0
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Starting point: symbol_scan_cntr[7] / Q
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Starting point: bttn_state_fifo[1] / Q
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Ending point: symbol_scan_cntr[7] / D
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Ending point: bttn_state_fifo[2] / D
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The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
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The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
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The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
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The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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Name Type Name Dir Delay Time Fan Out(s)
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-----------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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symbol_scan_cntr[7] FD1S3DX Q Out 0.559 0.559 -
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bttn_state_fifo[1] FD1S3JX Q Out 0.587 0.587 -
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symbol_scan_cntr[7] Net - - - - 2
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bttn_state_fifo[1] Net - - - - 3
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symbol_scan_cntr_s_0[7] CCU2C A0 In 0.000 0.559 -
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bttn_state_fifo[2] FD1S3JX D In 0.000 0.587 -
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symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.473 1.032 -
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====================================================================================
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symbol_scan_cntr_s[7] Net - - - - 1
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symbol_scan_cntr[7] FD1S3DX D In 0.000 1.032 -
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=========================================================================================
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##### END OF TIMING REPORT #####]
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##### END OF TIMING REPORT #####]
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