| Line 22... |
Line 22... |
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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|
|
ICG Latch Removal Summary:
|
ICG Latch Removal Summary:
|
Number of ICG latches removed: 0
|
Number of ICG latches removed: 0
|
Number of ICG latches not removed: 0
|
Number of ICG latches not removed: 0
|
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
|
syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
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|
|
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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|
|
|
|
|
|
Clock Summary
|
Clock Summary
|
*****************
|
*****************
|
|
|
Start Requested Requested Clock Clock Clock
|
Start Requested Requested Clock Clock Clock
|
Clock Frequency Period Type Group Load
|
Clock Frequency Period Type Group Load
|
--------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
|
display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
|
========================================================================================================
|
display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
|
|
=============================================================================================================================================================
|
|
|
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
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|
Finished Pre Mapping Phase.
|
Finished Pre Mapping Phase.
|
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|
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
| Line 53... |
Line 54... |
Pre-mapping successful!
|
Pre-mapping successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Tue Jan 17 01:19:11 2017
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# Wed Jan 18 01:08:15 2017
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###########################################################]
|
###########################################################]
|
