| Line 28... |
Line 28... |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
@N: MT206 |Auto Constrain mode is enabled
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
|
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| Line 44... |
Line 45... |
|
|
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
| Line 57... |
Line 58... |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
1 0h:00m:00s -0.76ns 6 / 13
|
|
2 0h:00m:00s -0.76ns 6 / 13
|
|
|
|
3 0h:00m:00s -0.62ns 7 / 13
|
|
|
|
|
|
4 0h:00m:00s -0.58ns 6 / 13
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
|
|
|
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
|
|
|
|
|
@S |Clock Optimization Summary
|
@S |Clock Optimization Summary
|
|
|
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
|
|
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
|
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
|
|
============================== Non-Gated/Non-Generated Clocks ===============================
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
---------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------
|
@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
|
@K:CKID0001 clk port 13 bttn_state
|
=============================================================================================
|
=======================================================================================
|
|
|
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
|
|
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Writing EDIF Netlist and constraint files
|
Writing EDIF Netlist and constraint files
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
L-2016.03L-1
|
L-2016.03L-1
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
|
|
|
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
|
|
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"
|
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
##### START OF TIMING REPORT #####[
|
# Timing Report written on Sun Jan 08 00:49:36 2017
|
# Timing Report written on Tue Jan 17 01:29:40 2017
|
#
|
#
|
|
|
|
|
Top view: DisplayDriverWrapper
|
Top view: DisplayDriverWrapper
|
Requested Frequency: 1297.0 MHz
|
Requested Frequency: 433.9 MHz
|
Wire load mode: top
|
Wire load mode: top
|
Paths requested: 5
|
Paths requested: 5
|
Constraint File(s):
|
Constraint File(s):
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
|
|
| Line 124... |
Line 133... |
|
|
Performance Summary
|
Performance Summary
|
*******************
|
*******************
|
|
|
|
|
Worst slack in design: -0.136
|
Worst slack in design: -0.407
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
Requested Estimated Requested Estimated Clock Clock
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
------------------------------------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0
|
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
====================================================================================================================================
|
==================================================================================================================================
|
|
|
|
|
|
|
|
|
|
|
| Line 143... |
Line 152... |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths -
|
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
===========================================================================================================================================
|
===========================================================================================================================================
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
| Line 169... |
Line 178... |
********************************
|
********************************
|
|
|
Starting Arrival
|
Starting Arrival
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
--------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136
|
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
==============================================================================================================
|
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
|
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
|
===================================================================================================================
|
|
|
|
|
Ending Points with Worst Slack
|
Ending Points with Worst Slack
|
******************************
|
******************************
|
|
|
Starting Required
|
Starting Required
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
---------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136
|
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
===============================================================================================================
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
|
================================================================================================================================
|
|
|
|
|
|
|
Worst Path Information
|
Worst Path Information
|
***********************
|
***********************
|
|
|
|
|
Path information for path number 1:
|
Path information for path number 1:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.501
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (critical) : -0.407
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 5
|
Starting point: DDwD_Top.ascii_reg[0] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[0] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[0] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 2:
|
Path information for path number 2:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[1] / Q
|
Starting point: symbol_scan_cntr[1] / Q
|
Ending point: DDwD_Top.ascii_reg[1] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 -
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[1] Net - - - - 1
|
symbol_scan_cntr[1] Net - - - - 15
|
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 3:
|
Path information for path number 3:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[2] / Q
|
Starting point: symbol_scan_cntr[2] / Q
|
Ending point: DDwD_Top.ascii_reg[2] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[2] Net - - - - 1
|
symbol_scan_cntr[2] Net - - - - 15
|
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 4:
|
Path information for path number 4:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[3] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[3] / D
|
Ending point: symbol_scan_cntr[5] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[3] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 5:
|
Path information for path number 5:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[4] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[4] / D
|
Ending point: symbol_scan_cntr[6] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[4] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
Constraints that could not be applied
|
Constraints that could not be applied
|
None
|
None
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
---------------------------------------
|
---------------------------------------
|
Resource Usage Report
|
Resource Usage Report
|
Part: lfe5u_45f-6
|
Part: lfe5um5g_45f-8
|
|
|
Register bits: 8 of 43848 (0%)
|
Register bits: 13 of 43848 (0%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 17
|
I/O cells: 19
|
|
|
|
|
Details:
|
Details:
|
FD1S3IX: 5
|
CCU2C: 5
|
|
FD1P3DX: 8
|
|
FD1S3AX: 1
|
FD1S3JX: 3
|
FD1S3JX: 3
|
GSR: 1
|
GSR: 1
|
IB: 2
|
IB: 3
|
OB: 15
|
IFS1P3JX: 1
|
|
INV: 2
|
|
OB: 16
|
|
ORCALUT4: 4
|
PUR: 1
|
PUR: 1
|
VHI: 2
|
ROM128X1A: 14
|
|
VHI: 1
|
VLO: 1
|
VLO: 1
|
false: 1
|
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Sun Jan 08 00:49:36 2017
|
# Tue Jan 17 01:29:40 2017
|
|
|
###########################################################]
|
###########################################################]
|
