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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [impl1_premap.srr] - Diff between revs 5 and 6

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Rev 5 Rev 6
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
 
 
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
 
 
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
 
 
ICG Latch Removal Summary:
ICG Latch Removal Summary:
Number of ICG latches removed:  0
Number of ICG latches removed:  0
Number of ICG latches not removed:      0
Number of ICG latches not removed:      0
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
 
 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
 
 
 
 
 
Clock Summary
Clock Summary
*****************
*****************
 
 
Start                        Requested     Requested     Clock        Clock                     Clock
Start                        Requested     Requested     Clock        Clock                     Clock
Clock                        Frequency     Period        Type         Group                     Load
Clock                        Frequency     Period        Type         Group                     Load
-----------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
DisplayDriverWrapper|bttn_state_derived_clock     1.0 MHz       1000.000      derived (from DisplayDriverWrapper|clk)     Autoconstr_clkgroup_0     8
=====================================================================================================
DisplayDriverWrapper|clk                          1.0 MHz       1000.000      inferred                                    Autoconstr_clkgroup_0     5
 
=========================================================================================================================================================
 
 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
 
 
Finished Pre Mapping Phase.
Finished Pre Mapping Phase.
 
 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
 
None
None
None
None
 
 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
 
 
Pre-mapping successful!
Pre-mapping successful!
 
 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
 
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Jan 08 00:49:34 2017
# Tue Jan 17 01:29:38 2017
 
 
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