URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [impl1_premap.srr] - Diff between revs 6 and 9

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Rev 6	Rev 9
Line 38...	Line 38...
`---------------------------------------------------------------------------------------------------------------------------------------------------------`	`---------------------------------------------------------------------------------------------------------------------------------------------------------`
`DisplayDriverWrapper\|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper\|clk) Autoconstr_clkgroup_0 8`	`DisplayDriverWrapper\|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper\|clk) Autoconstr_clkgroup_0 8`
`DisplayDriverWrapper\|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5`	`DisplayDriverWrapper\|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5`
`=========================================================================================================================================================`	`=========================================================================================================================================================`

`@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5\|Found inferred clock DisplayDriverWrapper\|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.`	`@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5\|Found inferred clock DisplayDriverWrapper\|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.`

`Finished Pre Mapping Phase.`	`Finished Pre Mapping Phase.`

`Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)`	`Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)`

Line 54...	Line 54...
`Pre-mapping successful!`	`Pre-mapping successful!`

`At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)`	`At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)`

`Process took 0h:00m:01s realtime, 0h:00m:01s cputime`	`Process took 0h:00m:01s realtime, 0h:00m:01s cputime`
`# Tue Jan 17 01:29:38 2017`	`# Tue Jan 17 23:41:22 2017`

`###########################################################]`	`###########################################################]`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [impl1_premap.srr] - Diff between revs 6 and 9