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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [report/] [DisplayDriverwDecoder_impl1_fpga_mapper_combined_clk.rpt] - Diff between revs 5 and 6

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Rev 5 Rev 6
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@S |Clock Optimization Summary
@S |Clock Optimization Summary
 
 
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
 
============================== Non-Gated/Non-Generated Clocks ===============================
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   8          DDwD_Top.ascii_reg[6]
@K:CKID0001       button              port                   9          symbol_scan_cntr[0]
=============================================================================================
===========================================================================================
 
 
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
##### END OF CLOCK OPTIMIZATION REPORT ######]
 
 

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