@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
