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<html><body><samp><pre>
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<html><body><samp><pre>
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<!@TC:1483829372>
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<!@TC:1484609376>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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#Hostname: DESKTOP-1AUKF7V
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# Sun Jan 08 00:49:32 2017
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# Tue Jan 17 01:29:36 2017
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#Implementation: impl1
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#Implementation: impl1
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<a name=compilerReport14></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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<a name=compilerReport9></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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@N: : <!@TM:1484609376> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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<a name=compilerReport15></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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<a name=compilerReport10></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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@N: : <!@TM:1484609376> | Running in 64-bit mode
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1483829372> | Setting time resolution to ns
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484609376> | Setting time resolution to ns
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Top entity is set to DisplayDriverWrapper.
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Top entity is set to DisplayDriverWrapper.
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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Options changed - recompiling
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VHDL syntax check successful!
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Synthesizing work.displaydriverwrapper.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Synthesizing work.displaydriverwrapper.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484609376> | Synthesizing work.displaydriverwdecoder_top.arch.
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1483829372> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:53:11:53:20:@W:CD638:@XP_MSG">DisplayDriverwDecoder_Top.vhd(53)</a><!@TM:1484609376> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1483829372> | Synthesizing work.displaydriverwdecoder_top.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ASCIIDecoder.vhd(15)</a><!@TM:1484609376> | Synthesizing work.asciidecoder.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484609376> | Synthesizing work.distromasciidecoder.structure.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484609376> | Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.distromasciidecoder.structure
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Post processing for work.asciidecoder.arch
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Post processing for work.displaydriverwdecoder_top.arch
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Post processing for work.displaydriverwdecoder_top.arch
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<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:38:8:38:17:@W:CL240:@XP_MSG">DisplayDriverwDecoder_Top.vhd(38)</a><!@TM:1483829372> | disp_data is not assigned a value (floating) -- simulation mismatch possible. </font>
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Post processing for work.displaydriverwrapper.arch
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Post processing for work.displaydriverwrapper.arch
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:20:8:20:14:@N:CL159:@XP_MSG">DisplayDriverWrapper.vhd(20)</a><!@TM:1483829372> | Input button is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(17)</a><!@TM:1484609376> | Input clk is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ASCIIDecoder.vhd(18)</a><!@TM:1484609376> | Input reset is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:29:8:29:13:@N:CL159:@XP_MSG">DisplayDriverwDecoder_Top.vhd(29)</a><!@TM:1484609376> | Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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# Tue Jan 17 01:29:36 2017
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###########################################################]
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###########################################################]
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<a name=compilerReport16></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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<a name=compilerReport11></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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@N: : <!@TM:1484609376> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609376> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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# Tue Jan 17 01:29:36 2017
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###########################################################]
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###########################################################]
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@END
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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# Tue Jan 17 01:29:36 2017
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###########################################################]
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###########################################################]
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<a name=compilerReport17></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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<a name=compilerReport12></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1483829374> | Running in 64-bit mode
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@N: : <!@TM:1484609377> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829374> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609377> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829374> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484609377> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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Process completed successfully.
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# Sun Jan 08 00:49:34 2017
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# Tue Jan 17 01:29:37 2017
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###########################################################]
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###########################################################]
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Pre-mapping Report
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Pre-mapping Report
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<a name=mapperReport18></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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<a name=mapperReport13></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1483829374> | No constraint file specified.
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@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484609378> | No constraint file specified.
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Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt:@XP_FILE">impl1_scck.rpt</a>
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Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt:@XP_FILE">impl1_scck.rpt</a>
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1483829374> | Running in 64-bit mode.
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484609378> | Running in 64-bit mode.
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1483829374> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484609378> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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ICG Latch Removal Summary:
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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<a name=mapperReport19></a>Clock Summary</a>
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<a name=mapperReport14></a>Clock Summary</a>
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*****************
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*****************
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Start Requested Requested Clock Clock Clock
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
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DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
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=====================================================================================================
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
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=========================================================================================================================================================
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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd:75:4:75:6:@W:MT529:@XP_MSG">displaydriverwdecoder_top.vhd(75)</a><!@TM:1483829374> | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:57:4:57:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(57)</a><!@TM:1484609378> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
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Finished Pre Mapping Phase.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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None
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None
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
|
|
Pre-mapping successful!
|
Pre-mapping successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Sun Jan 08 00:49:34 2017
|
# Tue Jan 17 01:29:38 2017
|
|
|
###########################################################]
|
###########################################################]
|
Map & Optimize Report
|
Map & Optimize Report
|
|
|
<a name=mapperReport20></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
|
<a name=mapperReport15></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
Product Version L-2016.03L-1
|
Product Version L-2016.03L-1
|
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
|
|
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1483829376> | Running in 64-bit mode.
|
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484609380> | Running in 64-bit mode.
|
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1483829376> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484609380> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
|
|
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| Line 166... |
Line 173... |
|
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|
|
Available hyper_sources - for debug and ip models
|
Available hyper_sources - for debug and ip models
|
None Found
|
None Found
|
|
|
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1483829376> | Auto Constrain mode is enabled
|
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484609380> | Auto Constrain mode is enabled
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:77:4:77:6:@N::@XP_MSG">displaydriverwrapper.vhd(77)</a><!@TM:1484609380> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
|
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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| Line 186... |
Line 194... |
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|
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
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| Line 199... |
Line 207... |
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
Pass CPU time Worst Slack Luts / Registers
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
1 0h:00m:00s -0.76ns 6 / 13
|
|
2 0h:00m:00s -0.76ns 6 / 13
|
|
|
|
3 0h:00m:00s -0.62ns 7 / 13
|
|
|
|
|
|
4 0h:00m:00s -0.58ns 6 / 13
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|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1483829376> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484609380> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
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|
|
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484609380> | Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
|
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|
|
|
@S |Clock Optimization Summary
|
@S |Clock Optimization Summary
|
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|
|
<a name=clockReport21></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
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<a name=clockReport16></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
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|
|
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
|
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
|
|
============================== Non-Gated/Non-Generated Clocks ===============================
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
---------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------
|
<a href="@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 8 DDwD_Top.ascii_reg[6]
|
<a href="@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 13 bttn_state
|
=============================================================================================
|
=======================================================================================
|
|
|
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
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|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
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|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
|
|
Writing EDIF Netlist and constraint files
|
Writing EDIF Netlist and constraint files
|
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1483829376> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484609380> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
L-2016.03L-1
|
L-2016.03L-1
|
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1483829376> | Synplicity Constraint File capacitance units using default value of 1pF
|
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484609380> | Synplicity Constraint File capacitance units using default value of 1pF
|
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|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
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|
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|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
|
|
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1483829376> | Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"</font>
|
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484609380> | Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
|
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|
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|
<a name=timingReport22></a>##### START OF TIMING REPORT #####[</a>
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<a name=timingReport17></a>##### START OF TIMING REPORT #####[</a>
|
# Timing Report written on Sun Jan 08 00:49:36 2017
|
# Timing Report written on Tue Jan 17 01:29:40 2017
|
#
|
#
|
|
|
|
|
Top view: DisplayDriverWrapper
|
Top view: DisplayDriverWrapper
|
Requested Frequency: 1297.0 MHz
|
Requested Frequency: 433.9 MHz
|
Wire load mode: top
|
Wire load mode: top
|
Paths requested: 5
|
Paths requested: 5
|
Constraint File(s):
|
Constraint File(s):
|
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1483829376> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484609380> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
|
|
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1483829376> | Clock constraints cover only FF-to-FF paths associated with the clock.
|
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484609380> | Clock constraints cover only FF-to-FF paths associated with the clock.
|
|
|
|
|
|
|
<a name=performanceSummary23></a>Performance Summary</a>
|
<a name=performanceSummary18></a>Performance Summary</a>
|
*******************
|
*******************
|
|
|
|
|
Worst slack in design: -0.136
|
Worst slack in design: -0.407
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
Requested Estimated Requested Estimated Clock Clock
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
------------------------------------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0
|
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
====================================================================================================================================
|
==================================================================================================================================
|
|
|
|
|
|
|
|
|
|
|
<a name=clockRelationships24></a>Clock Relationships</a>
|
<a name=clockRelationships19></a>Clock Relationships</a>
|
*******************
|
*******************
|
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.771 -0.136 | No paths - | No paths - | No paths -
|
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
===========================================================================================================================================
|
===========================================================================================================================================
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
|
|
<a name=interfaceInfo25></a>Interface Information </a>
|
<a name=interfaceInfo20></a>Interface Information </a>
|
*********************
|
*********************
|
|
|
No IO constraint found
|
No IO constraint found
|
|
|
|
|
|
|
====================================
|
====================================
|
<a name=clockReport26></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
|
<a name=clockReport21></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
|
====================================
|
====================================
|
|
|
|
|
|
|
<a name=startingSlack27></a>Starting Points with Worst Slack</a>
|
<a name=startingSlack22></a>Starting Points with Worst Slack</a>
|
********************************
|
********************************
|
|
|
Starting Arrival
|
Starting Arrival
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
--------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.853 -0.136
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.853 -0.136
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.853 -0.136
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.853 -0.136
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.853 -0.136
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.853 -0.136
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.853 -0.136
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.853 -0.136
|
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
==============================================================================================================
|
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
|
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
|
===================================================================================================================
|
|
|
|
|
<a name=endingSlack28></a>Ending Points with Worst Slack</a>
|
<a name=endingSlack23></a>Ending Points with Worst Slack</a>
|
******************************
|
******************************
|
|
|
Starting Required
|
Starting Required
|
Instance Reference Type Pin Net Time Slack
|
Instance Reference Type Pin Net Time Slack
|
Clock
|
Clock
|
---------------------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.717 -0.136
|
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.717 -0.136
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.717 -0.136
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.717 -0.136
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.717 -0.136
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.717 -0.136
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.717 -0.136
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.717 -0.136
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
===============================================================================================================
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
|
================================================================================================================================
|
|
|
|
|
|
|
<a name=worstPaths29></a>Worst Path Information</a>
|
<a name=worstPaths24></a>Worst Path Information</a>
|
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:21030:21297:@XP_NAMES_GATE">View Worst Path in Analyst</a>
|
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:23218:24892:@XP_NAMES_GATE">View Worst Path in Analyst</a>
|
***********************
|
***********************
|
|
|
|
|
Path information for path number 1:
|
Path information for path number 1:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.501
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (critical) : -0.407
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 5
|
Starting point: DDwD_Top.ascii_reg[0] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[0] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[0] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 2:
|
Path information for path number 2:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[1] / Q
|
Starting point: symbol_scan_cntr[1] / Q
|
Ending point: DDwD_Top.ascii_reg[1] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.853 0.853 -
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[1] Net - - - - 1
|
symbol_scan_cntr[1] Net - - - - 15
|
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 3:
|
Path information for path number 3:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[2] / Q
|
Starting point: symbol_scan_cntr[2] / Q
|
Ending point: DDwD_Top.ascii_reg[2] / D
|
Ending point: symbol_scan_cntr[7] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[2] Net - - - - 1
|
symbol_scan_cntr[2] Net - - - - 15
|
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 4:
|
Path information for path number 4:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[3] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[3] / D
|
Ending point: symbol_scan_cntr[5] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[3] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
Path information for path number 5:
|
Path information for path number 5:
|
Requested Period: 0.771
|
Requested Period: 2.305
|
- Setup time: 0.054
|
- Setup time: 0.211
|
+ Clock delay at ending point: 0.000 (ideal)
|
+ Clock delay at ending point: 0.000 (ideal)
|
= Required time: 0.717
|
= Required time: 2.094
|
|
|
- Propagation time: 0.853
|
- Propagation time: 2.442
|
- Clock delay at starting point: 0.000 (ideal)
|
- Clock delay at starting point: 0.000 (ideal)
|
= Slack (critical) : -0.136
|
= Slack (non-critical) : -0.348
|
|
|
Number of logic level(s): 0
|
Number of logic level(s): 4
|
Starting point: DDwD_Top.ascii_reg[4] / Q
|
Starting point: symbol_scan_cntr[0] / Q
|
Ending point: DDwD_Top.ascii_reg[4] / D
|
Ending point: symbol_scan_cntr[6] / D
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
|
|
Instance / Net Pin Pin Arrival No. of
|
Instance / Net Pin Pin Arrival No. of
|
Name Type Name Dir Delay Time Fan Out(s)
|
Name Type Name Dir Delay Time Fan Out(s)
|
---------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------
|
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.853 0.853 -
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
ascii_reg[4] Net - - - - 1
|
symbol_scan_cntr[0] Net - - - - 15
|
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.853 -
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
=======================================================================================
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
|
===========================================================================================
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
##### END OF TIMING REPORT #####]
|
|
|
Constraints that could not be applied
|
Constraints that could not be applied
|
None
|
None
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
|
|
---------------------------------------
|
---------------------------------------
|
<a name=resourceUsage30></a>Resource Usage Report</a>
|
<a name=resourceUsage25></a>Resource Usage Report</a>
|
Part: lfe5u_45f-6
|
Part: lfe5um5g_45f-8
|
|
|
Register bits: 8 of 43848 (0%)
|
Register bits: 13 of 43848 (0%)
|
PIC Latch: 0
|
PIC Latch: 0
|
I/O cells: 17
|
I/O cells: 19
|
|
|
|
|
Details:
|
Details:
|
FD1S3IX: 5
|
CCU2C: 5
|
|
FD1P3DX: 8
|
|
FD1S3AX: 1
|
FD1S3JX: 3
|
FD1S3JX: 3
|
GSR: 1
|
GSR: 1
|
IB: 2
|
IB: 3
|
OB: 15
|
IFS1P3JX: 1
|
|
INV: 2
|
|
OB: 16
|
|
ORCALUT4: 4
|
PUR: 1
|
PUR: 1
|
VHI: 2
|
ROM128X1A: 14
|
|
VHI: 1
|
VLO: 1
|
VLO: 1
|
false: 1
|
|
Mapper successful!
|
Mapper successful!
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
# Sun Jan 08 00:49:36 2017
|
# Tue Jan 17 01:29:40 2017
|
|
|
###########################################################]
|
###########################################################]
|
|
|
</pre></samp></body></html>
|
</pre></samp></body></html>
|
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No newline at end of file
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