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-- Entity: ASCIIDecoder
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-- Entity: ascii_decoder
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-- Date:2017-01-07
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-- Date:2017-01-07
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-- Author: GL
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-- Author: GL
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--
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--
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-- Description:
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-- Description:
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--! @brief ASCII decoding table with I/O control logic
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--! @brief ASCII decoding table with I/O control logic
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity ASCIIDecoder is
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entity ascii_decoder is
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port (
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port (
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clk : in std_logic; -- input clock, xx MHz.
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clk : in std_logic; --! input clock, xx MHz.
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reset : in std_logic;
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reset : in std_logic;
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--! ascii_in(7) represents the DP state so it is not decoded.
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--! ascii_in(7) represents the DP state so it is not decoded.
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--! Symbol codes from 0x00 to 0x7F are without DP lit. Symbol codes from 0x80 to 0xFF have DP lit.
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--! Symbol codes from 0x00 to 0x7F are without DP lit. Symbol codes from 0x80 to 0xFF have DP lit.
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ascii_in: in std_logic_vector(7 downto 0);
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ascii_in: in std_logic_vector(7 downto 0); --! input ascii code to be displayed
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disp_data_q : out std_logic_vector(14 downto 0)
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disp_data_q : out std_logic_vector(14 downto 0) --! decoded ascii code output with symbol bit map
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);
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);
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end ASCIIDecoder;
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end ascii_decoder;
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architecture arch of ASCIIDecoder is
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architecture arch of ascii_decoder is
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--! Q represents the symbol's bit mapping overlay over the 14-segment display.
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--! Q represents the symbol's bit mapping overlay over the 14-segment display.
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signal Q : std_logic_vector(13 downto 0);
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signal Q : std_logic_vector(13 downto 0);
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begin
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begin
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--! @details Decoding table
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--! @brief Decoding table handling all symbols except the DP
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rom_decoding_table: entity work.DistRomAsciiDecoder
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rom_decoding_table: entity work.decoder_table_dist_rom
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port map(
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port map(
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Address => ascii_in(6 downto 0),
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Address => ascii_in(6 downto 0),
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Q => Q
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Q => Q
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);
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);
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