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-- $Author: rpaley_yid $
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----------------------------------------------------------------------
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-- $Date: 2003-01-14 21:48:11 $
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---- ----
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-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
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---- Single port asynchronous RAM simulation model ----
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-- $Locker
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---- ----
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-- $Revision: 1.1.1.1 $
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---- This file is part of the single_port project ----
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-- $State: Exp $
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---- ----
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---- Description ----
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-- --------------------------------------------------------------------------
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---- This is a single port asynchronous memory. This files ----
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---- describes three architectures. Two architectures are ----
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---- traditional array based memories. One describes the memory ----
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---- as an array of STD_LOGIC_VECTOR, and the other describes ----
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---- the ARRAY as BIT_VECTOR. ----
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---- The third architecture describes the memory arranged as a ----
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---- linked list in order to conserve computer memory usage. The ----
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---- memory is organized as a linked list of BIT_VECTOR arrays ----
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---- whose size is defined by the constant PAGEDEPTH in ----
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---- single_port_pkg.vhd. ----
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---- ----
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---- Authors: ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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---- References: ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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--
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-- Purpose: This is a single port asynchronous memory. This files
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-- CVS Revision History
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-- describes three architectures. Two architectures are traditional
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-- array based memories. One describes the memory as an array of
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-- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR.
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-- The third architecture describes the memory arranged as a linked
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-- list in order to conserve computer memory usage. The memory
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-- is organized as a linked list of BIT_VECTOR arrays whose size
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-- is defined PAGEDEPTH in single_port_pkg.vhd.
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--
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
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-- initial checkin
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--
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--
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-- References:
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-- Revision 1.1 2003/01/14 17:48:31 Default
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-- 1. The Designer's Guide to VHDL by Peter Ashenden
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-- Initial revision
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-- ISBN: 1-55860-270-4 (pbk.)
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-- 2. Writing Testbenches - Functional Verification of HDL models by
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-- Janick Bergeron | ISBN: 0-7923-7766-4
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--
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--
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-- Notes:
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-- Revision 1.1 2002/12/24 18:09:05 Default
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-- Initial revision
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--
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--
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-- --------------------------------------------------------------------------
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LIBRARY IEEE;
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LIBRARY IEEE;
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LIBRARY WORK;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE WORK.single_port_pkg.ALL;
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USE WORK.single_port_pkg.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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USE WORK.linked_list_mem_pkg.ALL;
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ENTITY single_port IS
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ENTITY single_port IS
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GENERIC (
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GENERIC (
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rnwtQ : TIME := 1 NS
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rnwtQ : TIME := 1 NS);
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);
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PORT (
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PORT (
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d : IN data_inter_typ;
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d : IN STD_LOGIC_VECTOR;
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q : OUT data_inter_typ;
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q : OUT STD_LOGIC_VECTOR;
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a : IN addr_inter_typ;
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a : IN STD_LOGIC_VECTOR;
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rnw : IN STD_LOGIC;
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rnw : IN STD_LOGIC;
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dealloc_mem : IN BOOLEAN
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dealloc_mem : IN BOOLEAN := FALSE);
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);
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END ENTITY single_port;
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END ENTITY single_port;
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ARCHITECTURE ArrayMemNoFlag OF single_port IS
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ARCHITECTURE ArrayMemNoFlag OF single_port IS
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BEGIN
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BEGIN
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mem_proc : PROCESS
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mem_proc : PROCESS(d, a, rnw)
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TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ;
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TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF STD_LOGIC_VECTOR(d'RANGE);
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VARIABLE mem : mem_typ;
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VARIABLE mem : mem_typ;
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BEGIN
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BEGIN
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WAIT on rnw'transaction;
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IF ( rnw = '0') THEN -- Write
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IF ( rnw = '0') THEN -- Write
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mem(TO_INTEGER(unsigned(a))) := d;
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mem(TO_INTEGER(unsigned(a))) := d;
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ELSE -- Read
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ELSE -- Read
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q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
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q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ;
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END IF;
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END IF;
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END ArrayMemNoFlag;
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END ArrayMemNoFlag;
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ARCHITECTURE ArrayMem OF single_port IS
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ARCHITECTURE ArrayMem OF single_port IS
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BEGIN
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BEGIN
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mem_proc : PROCESS
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mem_proc : PROCESS(d, a, rnw)
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TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ;
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TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BIT_VECTOR(d'RANGE);
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TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN;
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TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN;
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VARIABLE mem : mem_typ;
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VARIABLE mem : mem_typ;
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VARIABLE flag : flag_typ;
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VARIABLE flag : flag_typ;
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BEGIN
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BEGIN
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WAIT ON rnw'transaction;
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IF ( rnw = '0') THEN -- Write
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IF ( rnw = '0') THEN -- Write
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mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
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mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d);
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flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
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flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag
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ELSE -- read data, either valid or 'U'
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ELSE -- read data, either valid or 'U'
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IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN
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IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN
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q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
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q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ;
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ELSE -- reading invalid memory location
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ELSE -- reading invalid memory location
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q <= (OTHERS => 'U') after rnwtQ;
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q <= (q'RANGE => 'U') after rnwtQ;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS mem_proc;
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END PROCESS mem_proc;
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END ArrayMem;
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END ArrayMem;
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ARCHITECTURE LinkedList OF single_port IS
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ARCHITECTURE LinkedList OF single_port IS
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CONSTANT WRITE_MEM : BOOLEAN := true;
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CONSTANT READ_MEM : BOOLEAN := false;
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BEGIN
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BEGIN
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mem_proc : PROCESS
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mem_proc : PROCESS(d, a, rnw, dealloc_mem)
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VARIABLE mem_page_v : mem_page_ptr;
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VARIABLE mem_page_v : mem_page_ptr;
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VARIABLE d_v : data_inter_typ;
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VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE);
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VARIABLE a_v : addr_typ;
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VARIABLE a_v : addr_typ;
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VARIABLE WRITE_MEM_v : BOOLEAN := true;
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VARIABLE READ_MEM_v : BOOLEAN := false;
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BEGIN
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BEGIN
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WAIT ON dealloc_mem'transaction , rnw'TRANSACTION;
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IF NOT dealloc_mem THEN
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IF NOT dealloc_mem THEN
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d_v := d;
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d_v := d;
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a_v := TO_INTEGER(unsigned(a));
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a_v := TO_INTEGER(unsigned(a));
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IF ( rnw = '0' ) THEN -- write to linked list memory
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IF ( rnw = '0' ) THEN -- write to linked list memory
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rw_mem( data => d_v,
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rw_mem( data => d_v,
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addr => a_v,
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addr => a_v,
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write_flag => WRITE_MEM_v,
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next_cell => mem_page_v,
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next_cell => mem_page_v
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write_flag => WRITE_MEM);
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);
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ELSE -- read from linked list memory
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ELSE -- read from linked list memory
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rw_mem( data => d_v,
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rw_mem( data => d_v,
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addr => a_v,
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addr => a_v,
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write_flag => READ_MEM_v,
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next_cell => mem_page_v,
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next_cell => mem_page_v
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write_flag => READ_MEM);
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);
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q <= d_v after rnwtQ;
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q <= d_v after rnwtQ;
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END IF;
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END IF;
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ELSE -- Deallocate memory from work station memory.
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ELSE -- Deallocate memory from work station memory.
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deallocate_mem(mem_page_v);
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deallocate_mem(mem_page_v);
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END IF;
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END IF;
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END PROCESS mem_proc;
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END PROCESS mem_proc;
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END LinkedList;
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END LinkedList;
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2003/01/14 17:48:31 Default
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-- Initial revision
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--
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-- Revision 1.1 2002/12/24 18:09:05 Default
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-- Initial revision
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--
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No newline at end of file
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No newline at end of file
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