| Line 47... |
Line 47... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Buses unconstrained, LGPL header added
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--
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-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
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-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
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-- initial checkin
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-- initial checkin
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--
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--
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-- Revision 1.1 2003/01/14 17:49:04 Default
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-- Revision 1.1 2003/01/14 17:49:04 Default
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-- Initial revision
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-- Initial revision
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| Line 78... |
Line 81... |
rnwtQ : TIME := 1 NS);
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rnwtQ : TIME := 1 NS);
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PORT (
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PORT (
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d : IN STD_LOGIC_VECTOR;
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d : IN STD_LOGIC_VECTOR;
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q : OUT STD_LOGIC_VECTOR;
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q : OUT STD_LOGIC_VECTOR;
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a : IN STD_LOGIC_VECTOR;
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a : IN STD_LOGIC_VECTOR;
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rnw : IN STD_LOGIC;
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nce : IN STD_LOGIC;
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nwe : IN STD_LOGIC;
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noe : IN STD_LOGIC;
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dealloc_mem : BOOLEAN);
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dealloc_mem : BOOLEAN);
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END COMPONENT single_port;
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END COMPONENT single_port;
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|
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COMPONENT tc_single_port IS
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COMPONENT tc_single_port IS
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PORT (
|
PORT (
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| Line 93... |
Line 98... |
CONSTANT ADDR_WIDTH : INTEGER := 16;
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CONSTANT ADDR_WIDTH : INTEGER := 16;
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|
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SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0);
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SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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SIGNAL rnw : STD_LOGIC;
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SIGNAL nce, nwe, noe : STD_LOGIC;
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SIGNAL dealloc_mem : BOOLEAN;
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SIGNAL dealloc_mem : BOOLEAN;
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SIGNAL to_srv : to_srv_typ;
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SIGNAL to_srv : to_srv_typ;
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SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
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SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE);
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SIGNAL tie_vdd : STD_LOGIC := '1';
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SIGNAL tie_vdd : STD_LOGIC := '1';
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BEGIN
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BEGIN
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dut : single_port
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dut : single_port
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PORT MAP (
|
PORT MAP (
|
d => d,
|
d => d,
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a => a,
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a => a,
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q => q,
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q => q,
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rnw => rnw,
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nce => nce,
|
|
nwe => nwe,
|
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noe => noe,
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dealloc_mem => dealloc_mem);
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dealloc_mem => dealloc_mem);
|
|
|
tc : tc_single_port
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tc : tc_single_port
|
PORT MAP (
|
PORT MAP (
|
to_srv => to_srv,
|
to_srv => to_srv,
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| Line 126... |
Line 133... |
REPORT "initialized"
|
REPORT "initialized"
|
SEVERITY NOTE;
|
SEVERITY NOTE;
|
WHEN read => -- perform memory read
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WHEN read => -- perform memory read
|
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
|
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
|
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
|
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
|
rnw <= '1';
|
nce <= '0';
|
|
noe <= '0';
|
|
nwe <= '1';
|
-- Wait for data to appear
|
-- Wait for data to appear
|
WAIT FOR ACCESS_DELAY;
|
WAIT FOR ACCESS_DELAY;
|
WHEN write => -- perform memory write
|
WHEN write => -- perform memory write
|
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
|
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length));
|
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
|
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length));
|
rnw <= '0';
|
nce <= '0';
|
|
noe <= '1';
|
|
nwe <= '0';
|
WAIT FOR ACCESS_DELAY;
|
WAIT FOR ACCESS_DELAY;
|
WHEN dealloc => -- deallocate the linked list for the LL architecture
|
WHEN dealloc => -- deallocate the linked list for the LL architecture
|
dealloc_mem <= true;
|
dealloc_mem <= true;
|
WHEN end_test => -- reached the end of the test case
|
WHEN end_test => -- reached the end of the test case
|
WAIT;
|
WAIT;
|
