Subversion Repositories single_port

<p align="right"><font size="3">B"H</font></p>

<p>A single port memory with testbench is described. The memory is

implemented as three different architectures.</p>

<p><span style="">A VHDL simulation model for an asynchronous single port

                        <td width="118">

                        <td width="118">                                       STD_LOGIC_VECTOR<br>

      <p>Input data bus, type specified in single_port_pkg</p>

      <p>Input data bus,&nbsp;unconstrained</p>

      <p>data_inter_typ</p>

      <p>STD_LOGIC_VECTOR<br>

      <p>Output data bus, type specified in single_port_pkg</p>

      <p>Output data bus,&nbsp;unconstrained</p>

      <p>addr_inter_typ</p>

      <p>STD_LOGIC_VECTOR<br>

      <p>Address bus, type specified in single_port_pkg</p>

      <p>Address bus, unconstrained</p>

<p>The single_port memory is implemented as three different

architecures. The first architecture is called ArrayMemNoFlag, and

<p><span style="">The first architecture is called ArrayMemNoFlag, and implements

implements the memory core as an array of STD_LOGIC_VECTOR. The memory

the memory core as an array of STD_LOGIC_VECTOR. This is the simplest architecture.

is asynchronous and triggered on rnw'transaction. When rnw = '0', the

It is provided for comparison with the models below but not recommended for

data on bus "d" is loaded into the memory at the location specified by

use in your design.<o:p></o:p></span></p>

the addres bus "a". When rnw = '1', the data located in memory address

"a" is loaded onto the output data bus "q". If a memory location is read

<p><span style="">The second architecture is called ArrayMem, and implements

which was not written to during the current simulation, 'U' are loaded

the memory core as an array of BIT_VECTOR. This arrangement allows less workstation

onto the memory bus.</p>

memory to be used than the ArrayMemNoFlag architecture. Use this architecture

<p>The second architecture is called ArrayMem, and implements the

 if most addresses in the simulated memory are written at least once.<o:p></o:p></span></p>

memory core as an array of BIT_VECTOR. This arrangement allows less

   <span style="">The third architecture is called LinkedList, and implements

workstation memory to be used than the ArrayMemNoFlag architecture. The

the memory core as a linked list of arrays of BIT_VECTOR. Each array in the

memory is asynchronous and triggered on rnw'transaction. When rnw = '0',

linked list is a page of memory whose size is specified in single_port_pkg.

the data on bus "d" is loaded into the memory at the location specified

This arrangement allows less workstation memory to be used than either the

by the addres bus "a". When rnw = '1', the data located in memory

ArrayMemNoFlag or ArrayMem architectures because memory representing the array

address "a" is loaded onto the output data bus "q". If a memory location

data is only allocated if the memory is actually written to. To de-allocate

is read which was not written to during the current simulation, 'U' are

the memory in the linked list, set dealloc_mem to true. Use this architecture

loaded onto the memory bus.</p>

if a significant portion of your simulated memory (which need not be contiguous)

<p>The third architecture is called LinkedList, and implements the

is never written to.<br>

memory core as a linked list of arrays of BIT_VECTOR. Each array in the

 <br>

linked list is a page of memory whose size is specified in

 All 3 architectures are asynchronous and triggered with any change of </span><span

single_port_pkg. This arrangement allows less workstation memory to be

 style="">d, a or rnw</span> (and dealloc_mem for the LinkedList architecture).

used than either the ArrayMemNoFlag or ArrayMem architectures. The

<span style="">When rnw = '0', the data on bus "d" is loaded into the memory

memory is asynchronous and triggered on rnw'transaction. When rnw = '0',

at the location specified by the addres bus "a". When rnw = '1', the data

the data on bus "d" is loaded into the memory at the location specified

located in memory address "a" is loaded onto the output data bus "q". If a

by the addres bus "a". When rnw = '1', the data located in memory

memory location is read which was not written to during the current simulation,

address "a" is loaded onto the output data bus "q". If a memory location

'U's are loaded onto the memory bus.</span><br>

is read which was not written to during the current simulation, 'U' are

<p>The single port memory is asynchronous and is triggered on

rnw'transaction. When rnw is cleared to '0', the write occurs at the

<p><span style="">The single port memory is asynchronous and is triggered

same time as rnw'transaction. When a read occurs, with rnw = '1' , data

on any change of d, a or rnw. When rnw is cleared to '0', the write occurs

appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample

at the same time as rnw'transaction. When a read occurs, with rnw = '1' ,

timing diagram illustrates both a read and write operation.</p>

data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample

 width="958" height="251" border="0"><br clear="left">

 width="958" height="251" border="0">

<p>The test bench is arranged as a client server architecture as

specified by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"

<p>The test bench is arranged as a client server architecture as specified

 href="#sdfootnote1sym"><sup>1</sup></a>. A diagram illustrating the

by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"

testbench is given below.<br>

 href="#sdfootnote1sym"><sup>1</sup></a>. A diagram illustrating the testbench

 width="838" height="371" border="0"><br clear="left">

 width="838" height="371" border="0">

Two tests are specified in tc_single_port component. The first test

 <br clear="left">

writes data to two logical memory pages, and then reads them back

  Two tests are specified in tc_single_port component. The first test writes

verifying the correct data. The test case writes an error message to the

data to two logical memory pages, and then reads them back verifying the correct

console for every miscompare. The second case verifies that the

data. The test case writes an error message to the console for every miscompare.

single_port memory model outputs unknowns to the q bus if a read occurs

The second case verifies that the single_port memory model outputs unknowns

for an unwritten memory location. Six configurations are specified in

to the q bus if a read occurs for an unwritten memory location. Six configurations

the test bench architecture tb_single_port, running both tests for each

are specified in the test bench architecture tb_single_port, running both

single_port architecture. <br>

tests for each single_port architecture. <br>

<p>A Makefile is used to compile and run all of the tests in a Unix or

like environment, such as Cygwin. The compilation and simulation is

<p>A Makefile is used to compile and run all of the tests in a Unix or like

targetted to the SymphonyEDA tool available at <a

environment, such as Cygwin. The compilation and simulation is targetted to

 href="www.symphonyeda.com">www.symphonyeda.com</a> .</p>

the SymphonyEDA tool available at <a href="http://www.symphonyeda.com">www.symphonyeda.com</a>.</p>